Don Bosco Institute of Technology, Kurla

Academic Year 2024-25

EXPERIMENT NO: 5

Title: To implement ripple carry adder

Name of student: Sayali Kulkarni

Roll No: 59
Div: A
Batch: C

Class: S.E Comps (Sem III) Lecturer: Sejal M Chopra

Subject: DLCA Lab
 Don Bosco Institute of Technology, Kurla
Academic Year 2024-25

EXPERIMENT NO: 5
To implement ripple carry adder
AIM To simulate ripple carry adder circuit using LOGISIM.
LEARNING To learn building of combinational circuit and then evaluate itsoutput.
OBJECTIVE

LEARNING
OUTCOME Students can simulate the operation of ripple carry adder

LAB CSL 302.4: Ability to design the basic building blocks of acomputer: adders
OUTCOME

PROGRAM PO1-1,
OUTCOME PO5-2,
PO8-3,
PO9-3, PO12-2,
PSO1-1

BLOOM'S Analyze
TAXONOY
LEVEL
THEORY Ripple carry Adder
 Ripple Carry Adder is a combinational logic circuit.
 It is used for the purpose of adding two n-bit binary numbers.
 It requires n full adders in its circuit for adding two n-bit binary numbers.
 It is also known as n-bit parallel adder.

 Ripple Carry Adder works in different stages.

 Each full adder takes the carry-in as input and produces carry-out and sum bit as
output.
 The carry-out produced by a full adder serves as carry-in for its adjacent most
significant full adder.
 When carry-in becomes available to the full adder, it activates the full adder.
 After full adder becomes activated, it comes into operation.

Working:
 The two 4-bit numbers are 0101 (A3A2A1A0) and 1010 (B3B2B1B0).
 These numbers are to be added using a 4-bit ripple carry adder.

4-bit Ripple Carry Adder-

In Mathematics, any two 4-bit binary numbers A3A2A1A0 and B3B2B1B0-

 Don Bosco Institute of Technology, Kurla
Academic Year 2024-25

Using ripple carry adder, this addition is carried out as shown by the following logic
diagram-

Stage-01:
 When Cin is fed as input to the full Adder A, it activates the full adder A.
 Then at full adder A, A0 = 1, B0 = 0, Cin = 0.

Full adder A computes the sum bit and carry bit as-
Calculation of S0–
S0 = A0 ⊕ B0 ⊕ Cin
S0 = 1 ⊕ 0 ⊕ 0
S0 = 1
 Don Bosco Institute of Technology, Kurla
Academic Year 2024-25

Calculation of C0–
C0 = A0B0 ⊕ B0Cin ⊕ CinA0
C0 = 1.0 ⊕ 0.0 ⊕ 0.1
C0 = 0 ⊕ 0 ⊕ 0
C0 = 0

Stage-02:
 When C0 is fed as input to the full adder B, it activates the full adder B.
 Then at full adder B, A1 = 0, B1 = 1, C0 = 0.

Full adder B computes the sum bit and carry bit as-

Calculation of S1–
S1 = A1 ⊕ B1 ⊕ C0
S1 = 0 ⊕ 1 ⊕ 0
S1 =1

Calculation of C1–
C1 = A1B1 ⊕ B1C0 ⊕ C0A1
C1 = 0.1 ⊕ 1.0 ⊕ 0.0
C1 = 0 ⊕ 0 ⊕ 0
C1 = 0

Stage-03:
 When C1 is fed as input to the full adder C, it activates the full adder C.
 Then at full adder C, A2 = 1, B2 = 0, C1 = 0.

Full adder C computes the sum bit and carry bit as-

Calculation of S2–
S2 = A2 ⊕ B2 ⊕ C1
S2 = 1 ⊕ 0 ⊕ 0
S2 = 1

Calculation of C2–
C2 = A2B2 ⊕ B2C1 ⊕ C1A2
C2 = 1.0 ⊕ 0.0 ⊕ 0.1
C2 = 0 ⊕ 0 ⊕ 0
C2 = 0

Stage-04:
 When C2 is fed as input to the full adder D, it activates the full adder D.
 Then at full adder D, A3 = 0, B3 = 1, C2 = 0.
 Don Bosco Institute of Technology, Kurla
Academic Year 2024-25

Full adder D computes the sum bit and carry bit as-

Calculation of S3–
S3 = A3 ⊕ B3 ⊕ C2
S3 = 0 ⊕ 1 ⊕ 0
S3 = 1

Calculation of C3–
C3 = A3B3 ⊕ B3C2 ⊕ C2A3
C3 = 0.1 ⊕ 1.0 ⊕ 0.0
C3 = 0 ⊕ 0 ⊕ 0
C3 = 0

Thus finally,
 Output Sum = S3S2S1S0 = 1111
 Output Carry = C3 = 0

Adavntages-

Simplicity: RCAs are straightforward to design and implement, making them easy to
understand and use in various applications.
 Low Hardware Cost: They require fewer components than more complex adders (like carry-
lookahead adders), leading to a lower overall hardware cost.
 Scalability: RCAs can be easily scaled to add more bits simply by adding more full adder stages,
making them flexible for different applications.
 Less Propagation Delay: In small-scale applications, the delay introduced by RCAs may be
acceptable, especially for operations where speed is not critical.
 Easy Integration: Due to their simple structure, RCAs can be easily integrated into larger systems
without requiring complex interfacing.
 Less Power Consumption: Compared to more advanced adder designs, RCAs typically consume
less power, especially in low-speed applications.

Disadvantages-
 Each full adder has to necessarily wait until the carry bit becomes available from its adjacent
full adder.
 This increases the propagation time.
 Ripple Carry Adder does not allow to use all the full adders simultaneously.
 Due to this reason, ripple carry adder becomes extremely slow.
 This is considered to be the biggest disadvantage of using ripple carry adder.

SOFTWARE logisim-win-2.7.1 software

USED
PROBLEM Problem statement:
STATEMENTS 1. Implement ripple carry adder circuit.
 Don Bosco Institute of Technology, Kurla
Academic Year 2024-25

OUTPUT Full Adder:-

Test Cases:-
1)

2)
 Don Bosco Institute of Technology, Kurla
Academic Year 2024-25

CONCLUSION In conclusion, the simulation of the Ripple Carry Adder circuit using LOGISIM
successfully demonstrates the design and functioning of a basic multi-bit binary adder.
The Ripple Carry Adder was implemented by cascading several full adders, where each
carry-out from a previous bit is used as the carry-in for the next higher bit. This
simulation helps in understanding the propagation delay, as the addition process
depends on the carry signal propagating through each stage of the full adders. The
delay grows linearly with the number of bits, highlighting the trade-off between
simplicity and speed in the Ripple Carry Adder design. This experiment reinforces
foundational concepts in digital circuits and provides insights into improving
performance through more advanced designs like carry-lookahead adders.
REFERENCES 1. https://www.gatevidyalay.com/ripple-carry-adder/
2. R. P. Jain, “Modern Digital Electronic”, McGraw-Hill Publication,4th Edition.
3. https://www.youtube.com/watch?v=OkzoRnjOuNw

Class: S.E Comps (Sem III) Lecturer: Sejal M Chopra

Subject: DLCA Lab