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AvadheshDixitLecture 15 ComputerOrganisation

The document describes the organization of CPU registers, highlighting key registers such as the accumulator, data register, instruction register, address register, and program counter. It explains how a bus system connects multiple registers to an ALU for efficient data transfer and micro-operations, detailing the role of multiplexers and decoders in this process. Control signals generated by the control unit manage the flow of information within the CPU during clock cycles.

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2 views3 pages

AvadheshDixitLecture 15 ComputerOrganisation

The document describes the organization of CPU registers, highlighting key registers such as the accumulator, data register, instruction register, address register, and program counter. It explains how a bus system connects multiple registers to an ALU for efficient data transfer and micro-operations, detailing the role of multiplexers and decoders in this process. Control signals generated by the control unit manage the flow of information within the CPU during clock cycles.

Uploaded by

ShivuAg
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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General Register Organization:

The number of registers in a processor unit may vary from just one processor register to as many as 64
registers or more.
1. One of the CPU registers is called as an accumulator AC or 'A' register. It is the main operand
register of the ALU.
2. The data register (DR) acts as a buffer between the CPU and main memory. It is used as an input
operand register with the accumulator.
3. The instruction register (IR) holds the opcode of the current instruction.
4. The address register (AR) holds the address of the memory in which the operand resides.
The program counter (PC) holds the address of the next instruction to be fetched for execution.
Additional addressable registers can be provided for storing operands and address. This can be viewed
as replacing the single accumulator by a set of registers. If the registers are used for many purpose, the
resulting computer is said to have general register organization. In the case of processor registers, a
registers is selected by the multiplexers that form the buses.
When a large number of registers are included in the CPU, it is most efficient to connect them through a
common bus system. The registers communicate with each other not only for direct data transfers, but
also while performing various micro-operations. Hence it is necessary to provide a common unit that can
perform all the arithmetic, logic and shift micro-operation in the processor.

A Bus organization for seven CPU registers:


The output of each register is connected to true multiplexer (mux) to form the two buses A & B. The
selection lines in each multiplexer select one register or the input data for the particular bus. The A and B
buses forms the input to a common ALU. The operation selected in the ALU determines the arithmetic or
logic micro-operation that is to be performed. The result of the micro-operation is available for output and
also goes into the inputs of the registers. The register that receives the information from the output bus is
selected by a decoder. The decoder activates one of the register load inputs, thus providing a transfer
both between the data in the output bus and the inputs of the selected destination register.
The control unit that operates the CPU bus system directs the information flow through the registers and
ALU by selecting the various components in the systems.
R1 ® R2 + R3
(1) MUX A selection (SEC A): to place the content of R2 into bus A
(2) MUX B selection (sec B): to place the content of R3 into bus B
(3) ALU operation selection (OPR): to provide the arithmetic addition (A + B)
(4) Decoder destination selection (SEC D): to transfer the content of the output bus into R1
These form the control selection variables are generated in the control unit and must be available at the
beginning of a clock cycle. The data from the two source registers propagate through the gates in the
multiplexer and the ALU, to the output bus, and into the into of the destination registers, all during the
clock

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