1

Assignment 4 Spring 2024

1. Following is the table for NOR BASED S-R Latch? Use the table to process all 8 possible cases
for the GATED S_R Latch?
NOTE: Process each & every gate in all 8 cases

,--0- ·•
R Ut
-.
Input Output
l
I
Ot+l s R Ot+1
u I 0 0 01
I
-

0
I
0 1 0
L__s-· Ot
1 0 1
-
'
1 1 invalid
Ot+l

CASEI CASE-II
S=0,R=0,E=l,Q=0 S=0,R=0,E=l,Q=l
0 I
0 I
E E
I e,
I 0

S=l,R=0,E==l,Q=0 S=l,R=0,E=l,Q=l
d
p r
f
E E

1
 "·
��
� .s

al
....'<:I- cS �e
Q..
�
Ec::: -.s...., �g
Q,

-Si!' � -g
Assignment 4 Spnn
�
� e -.s
\J

Q..
....

Q, 0:::
G
13 '2111
,._

S =O,R=l,E=l,Q=O
R
0
o,
-..
E E
I.
J
S=l,R=l,E=l,Q=l
,
S=l,R=l,E=l,Q=O
R
0 ()

E tJ

0
, �
(')

TABLE:

INPUT OUTPUT
E s R Qr+1
X X
0
1 0 0
.. t':J+
iD�
I
--- 1 0
------· ----�- 1
0
1 1 J
1 -- ----1 - 1 TAvahJ ;.. nc,I-,
I

... --·--- ----

;::
!::'

..
Assignment 4 Spring 2c.

Following is the roble for NANO BASED 5-R Latch? Use the table to process al/ 8 possible
cases for the GATED S_R Latch?
NOTE: Process each & every gate in all 8 coses

-
s " INPUT I OUTPUT
1
\

•I Ot
-
s R
C

I_) -
Ot+1

0 0 I
Q t+l
X I
Q t+l
t -� J'
[- - 0 1 ) I (j

- 2
\
I
0 •
Ot
1 I 0 0 }
,R __
J

Ot,1
T_ 1 I 1 I ee� at;
;,i:..1� ile ev-vd --;)
• Process the POSITVE CLOCK EDGE JK FLIP FLOP circuit given below for all possible cases and
fill the table accordingly?

NOTE: Process each and every block no marks will be given for direct answer. No need to process
NANO LATCH use table filled in Port A

------------------------
CIRC IT:
CLK-0 CLK=l

;-u-
J]�0l n0
- ! a
LJT
· I----------
CLK ·•, �--..Ji
I
K ---�
�� �: Q