Module 5 Synchronization

Dr. S. D. Ruikar
 Syllabus
Synchronization Fundamentals, Applications of
synchronization (Arbitration of asynchronous signals,
Sampling asynchronous signals, Crossing clock domains),
Synchronization failure and meta-stability, Synchronizer
Design (Mesochronous, Plesiochronous, Periodic
Asynchronous)
 Clock domains
Mesochronous
same frequency but different phases
Plesiochronous
slightly different frequencies
Periodic
clearly different frequencies, but the phase difference is periodic
Asynchronous
clearly different frequenciens without a periodic phase difference
Comparison of three Synchronous strategies

Figure: three approaches to Synchronous a system

Synchronization —The Basic Idea
 Synchronizer determines the order
of events on two signals
– which one of the signals A and B
had a transition first ?
 Is the order of these events
important?
– if it is not, we do not actually
need synchronization
 Often one of the signals is data
and the other a clock which
samples the data
– did the data change after or before
the rising edge of the clock?
– what if they changed
simultaneously?

 Synchronization is not a trivial operation, because the time it takes to

decide which signal came first is unbounded, if the events are practically
simultaneous
 Arbitration of Asynchronous Signal

Sampling of Asynchronous Signal

Crossing clock domains

 Uses of Synchronization
 Arbitration of mutually asynchronous
AReq AGrant
signals
– requests for a shared resource (bus, BReq BGrant
memory, functional unit, ... )

 Sampling asynchronous signals with a

clock XAsync Sync XSync
– e.g. real-world input devices such as
sensors, event detectors, switches, …
Clk

 Crossing clock domains

– sampling a synchronous signal of a clock XA XB
domain with a different clock of another Module A Sync Module B
clock domain
– how problematic this is depends on the
relationship between the two clocks
» do they have a same frequency with a ClkA ClkB
phase shift?
» are they periodic?
Synchronization Failure
 Which one of the signals A and B had a
transition first ?
 The closer the events are, the more
difficult it is to decide the order
 If the events are very close to each other,
within the sampling window of the
device, the synchronizer may enter a
metastable state
 Metastable state may be interpreted either
as 0 or 1 or something between 0 and 1 by
the circuits connected to the synchronizer
outputs
 Fundamental problem is that the
synchronizer may stay in the metastable
state for an arbitrary long time period !
– how many clock periods I am willing wait
to be ―sure that metastability has ended?
 NAND Arbiter
 NAND arbiter is a simple SR latch
– assume that initially the inputs A and B are
both low, and the outputs Afirst’ and
Bfirst’ are both high
 If an up-going transition on A arrives a
NAND delay (or more) earlier than on B,
Afirst’ goes low locking Bfirst’ to the
initial high state
 If an up-going transition on B arrives a
NAND delay (or more) earlier than on A,
Bfirst’ goes low locking Afirst’ to the
initial high state
 If the separation between the transitions is less than a NAND delay, both outputs start
to go low, but the output of the later signal returns eventually to the initial high state and
the output of the earlier signal continues to the low state
 If the input transitions are simultaneous, we have a true metastable situation, where the
final result of the arbitration is unknown
– in theory, both outputs may stay at the metastable voltage VDD / 2 forever
– in practice, eventually one of the outputs go high and the other low due to noise !
 NAND Arbiter
 When the inputs A and B rise
almost simultaneously, the initial 1 (unit voltage)
change V1 in the differential
output voltage is proportional to
the delay t between A and B:
V1 = Ks t  t / ta 1 (unit voltage)
Here ta is the aperture time of the
NAND latch, and the constant Ks
is defined as
Ks = I / C  1 / ta
 NAND Arbiter
 Initial voltage difference V1 is
exponentially amplified to the full 1 (unit voltage)
swing by the sense amp-lifier
formed by the cross-coupled
NAND gates:
V ( t ) = V1 exp(t / s) 1 (unit voltage)
Here s is the regeneration time
constant of the sense amplifier
 Decision time td to attain the unit
voltage V (td ) = 1 is then given
as
1
td = – s ln(V1 )
 Note that if V1 is zero, i.e., the
transitions on A and B are exactly
simultaneous, the decision time td 1
becomes infinite
– metastable state (V = 0) td
 Static Flip-Flops Behave Similarly !
 Initial voltage difference V1
between the outputs of the cross-
coupled inverters depends on the
delay t between a transition at
the data input D and the locking
edge of the clock
 Initial voltage difference is
expontentially amplified after the
locking edge of the clock
V1
transmission
gates

D Q
Brute-Force (Waiting) Synchronizer
 Synchronizes the asynchronous input A
to the clock Clk
 First flip-flop FF1 samples A
– may go into a metastable state,
depending on the timing of A and Clk
 Then we await the possible metastable
state to end for a waiting period tw
 Usually the waiting time is one clock
cycle, which means that the output of
FF1 is sampled by the second flip-flop
FF2 to generate the final synchronized
signal AS
 In general, to implement an N-cycle
waiting period, we need N casca-ded
flip-flops in addition to the sampling
flip-flop FF1
 Total synchronization latency is N+1
clock cycles
Brute-Force Synchronization Failure
 What if the first flip-flop FF1 is
still in a metastable state after the
one-cycle waiting period ?
– second flip-flop FF2 samples a
metastable state !

 What is the probability of this

unfortunate situation to occur ? Metastable (VDD / 2)

 In general, the probability of

Metastable (VDD / 2)
synchronization failure can be
calculated as follows:

P (failure) = P (enter metastable state) · P (still in metastable state after tw)

or
PF = PE · PS
Probability of Entering a Metastable State
 Flip-flop can enter a metastable state, when its data input D changes the state during the
aperture time or sampling window of the flip-flop
 Probability of an input transition to occur during the sampling window is computed by
dividing the apeture time ta by the clock period tcy

ta
PE   ta fClk
tcy
 Probability of Staying in the Metastable State
 Flip-flop is still in the metastable state after the waiting period tw , if the initial voltage
difference V1 was too small to be exponentially amplified to the full value 1 during the
waiting period. Hence, the final value VF is smaller than 1.
 Probability of this to happen is defined to be the ratio of such a small initial difference
V1 to the corresponding final value VF

t 
VF  V1 exp  w 
  s
VF =1 
V1  tw 
V1 PS   exp  
V F  s
Failure Probability and Frequency
 Synchronization failure probability PF is the product of the probabilities of entering and
staying in the metastable state PE and PS
 Potentially, every event at the flip-flop data input D can cause a synchronization failure
with the probability PF
 Hence, the synchronization failure frequency (synchronization error rate) fF is calculated
by multiplying the failure probability PF by the event frequency fD

 t w 
PF  PE PS  t a f Clk exp
 s
 t w 
f F  f D PF  t a f D f Clk exp
 s

VF =1

V1
 Two Synchronizer Calculation Examples
 Assume that a 1 MHz data signal (fD) is
sampled with a 100 MHz clock signal
(fClk)
 Aperture time ta and the regene-ration
time constant s of the sampling flip-flop
are both 200 ps
 Waiting period tw is one clock cycle (we
have the second flip-flop):
tw = 1/ fClk = 10 ns
 Two Synchronizer Calculation Examples
 Assume that a 1 MHz data signal (fD) is
sampled with a 100 MHz clock signal
(fClk)
 Aperture time ta and the regene-ration
time constant s of the sampling flip-flop
are both 200 ps
 Waiting period tw is one clock cycle (we
have the second flip-flop):
tw = 1/ fClk = 10 ns
 We get:
PE = 0.02
PS = 1.94·10 -22
PF = 3.88·10 -24
fF = 3.88·10 -18 Hz
MTBF = 1/ fF = 2.58·10 17 s
= 8.2 ·10 9 years
Mean Time Between Failures
 Two Synchronizer Calculation Examples
 Assume that a 1 MHz data signal (fD) is  Assume that a 10 MHz data signal (fD)
sampled with a 100 MHz clock signal is sampled with a 500 MHz clock signal
(fClk) (fClk)
 Aperture time ta and the regene-ration  Aperture time ta and the regene-ration
time constant s of the sampling flip-flop time constant s of the sampling flip-flop
are both 200 ps are both 100 ps
 Waiting period tw is one clock cycle (we  Waiting period tw is one clock cycle (we
have the second flip-flop): have the second flip-flop):
tw = 1/ fClk = 10 ns tw = 1/ fClk = 2 ns
 We get:
PE = 0.02
PS = 1.94·10 -22
PF = 3.88·10 -24
fF = 3.88·10 -18 Hz
MTBF = 1/ fF = 2.58·10 17 s
= 8.2 ·10 9 years
Mean Time Between Failures
 Two Synchronizer Calculation Examples
 Assume that a 1 MHz data signal (fD) is  Assume that a 10 MHz data signal (fD)
sampled with a 100 MHz clock signal is sampled with a 500 MHz clock signal
(fClk) (fClk)
 Aperture time ta and the regene-ration  Aperture time ta and the regene-ration
time constant s of the sampling flip-flop time constant s of the sampling flip-flop
are both 200 ps are both 100 ps
 Waiting period tw is one clock cycle (we  Waiting period tw is one clock cycle (we
have the second flip-flop): have the second flip-flop):
tw = 1/ fClk = 10 ns tw = 1/ fClk = 2 ns
 We get:  We get:
PE = 0.02 PE = 0.05
PS = 1.94·10 -22 PS = 2.07·10 -9
PF = 3.88·10 -24 PF = 1.04·10 -10
fF = 3.88·10 -18 Hz fF = 1.04·10 -3 Hz
MTBF = 1/ fF = 2.58·10 17 s MTBF = 1/ fF = 961 s
= 8.2 ·10 9 years = 16 min !!
Mean Time Between Failures
 Common Synchronizer Mistakes
 Common mistake in synchronizer
design is to make the regeneration time
constant s of the sampling device large
by
– using a dynamic flip-flop
» s is infinitive (no regeneration at
all ! ) D Q
– driving a load with the feedback loop
directly
» load capacitance increases the
effective regeneration time constant
significantly Q
D
 load capacitance may be 20 times
the internal capacitance
» for example, if the time constant is Cload
increased from 200 ps to 4 ns,  t w 
MTBF decreases from 8 billion PF  PE PS  ta fClk exp
years to 0.6 ms  s
 t 
f F  f D PF  t a f D f Clk exp w 
 s
 Correct Implementation
 Correct way to implement a
synchronizer is to
– use static latches/flip-flops with
feedback loops
– isolate the driven load capacitance from
the feedback loop by appropriate
buffering

Clk’

Q
Clk

Cload
 Completion Detection
 It is not possible to bound the synchronizer settling time, because in theory a
metastable state may last forever
– so you just have to decide how many clock cycles make a sufficient/safe waiting period
 However, it is possible to detect when the synchronizer has been settled !
 Consider the below circuit (Vd = decision voltage)
– upper comparator’s output goes high when V < -Vd
– lower comparator’s output goes high when V > Vd
– both outputs are low when -Vd < V < Vd
 This can be exploited only in the asynchronous (self-timed) design style
– no use in synchronous (clocked) design !

AFirst

– AFirst
V
+
+Vd -
Done BFirst

–
+ BFirst
+Vd -
 Classification of Signal-Clock Synchronization
 Synchronous  Periodic
– signal has the same frequency and phase – signal and clock have arbitrary
as the clock frequencies but the phase difference is
– it is safe to sample the signal directly periodic
with the clock (synchronizer is not – this information can be used to predict
needed) which signal events occur during the
 Mesochronous unsafe portion of the clock, i.e., close to
the sampling edge of the clock
– signal has the same frequency as the
clock but is potentially out of phase,  Asynchronous
with an phase difference c – signal is not periodic, which means that
– it is safe to sample the signal if the clock the signal events may occur at arbitrary
or signal is delayed by a constant times
amount – full brute-force synchronizer is needed !
 Plesiochronous
– signal and clock have nearly the same
frequency, and hence the phase
difference varies slowly XAsync Sync XSync
– it is safe to sample the signal if the clock
or signal is delayed by a variable
amount Clk
 Synchronization Hierarchy
 Difficulty of synchronization depends
on the relationship between the clock
and the signal to be sampled
 Synchronous
– signal events are always outside the
keep-out region of the clock
 Mesochronous
– unknown but constant phase diffe-rence
between the signal and the clock events
 Plesiochronous
– phase difference varies slowly
 Periodic
– phase difference is periodic
– includes mesochronous and
plesiochronous cases
 Asynchronous
– signal events are arbitrary with respect
to clock events
 Brute-Force Synchronizer
 Synchronizers can be compared in terms
of
– synchronizer delay tz
– failure rate fF
 For the brute-force synchronizer:
Inherent
t Amax
t z  t w  2t dCQ  cy synchronization
delay
2 Aavg
 t 
f F  t a f D f Clk exp w  Amin
 s 
Clk
 Can we get rid of the waiting period
min = 0
tw ?
avg = tcy / 2
max = tcy

Average time from A to the next

sampling clock edge is tcy / 2
(inherent synchronization delay)
 General Issues on Periodic Synchronizers
 If an input signal is synchronized to some periodic transmitter clock, we have a periodic
synchronization at the receiver. Mesochronous and plesiochronous are just special cases
of this:
– mesochronous : transmitter and receiver clock frequencies are exactly equal
– plesiochronous : transmitter and receiver clock frequencies are almost equal
 Periodicity means that we know in advance, if the signal is safe to be sampled at a given
receiver clock edge
– if it is safe, we just sample the signal normally
– if it is not safe, we first delay the signal or the receiver clock to make the signal safe
 Hence, the waiting time tw can be removed from the signal path
– periodic synchronizer is faster than a brute-force synchronizer
– it is also more reliable, because the obligatory waiting is done either once or in parallel with
sampling data, indicating that the waiting time tw can be made large
Safe and Unsafe Periods
Mesochronous Synchronization
 Constant phase difference between the sampling clock and the received signal
– the transmitter of the signal is actually synchronized to the same master clock as the
receiver, but there is a significant skew
» skew in the clock distribution network
» delay of the signal wire, if the transmitter and the receiver are relatively far from
each other
– typical situation in a large system which uses synchronous open-loop timing
» no skew control as in closed-loop timing
 This means that we have to synchronize only once, i.e., when the system is
initialized! Hence, during system reset we measure the phase difference
– If it is OK, the signal can be sampled directly forever
– If it is not OK, the phase difference is made safe by delaying the signal or the clock —
then the signal can be sampled forever
– this initial phase check is the only asynchronous event we ever sample, and hence we can
afford to wait a long time for a possible metastable state to end !
Delay-Line Synchronizer
 Suitable for both mesochronous and
plesiochronous synchronization
 Idea is to delay the signal as needed to
keep the signal transitions outside the
keep-out region of the receiver clock
 Average delay of this synchronizer is
tv
t
t z  tv  tdCQ  cy

2
variable delay line
 Delay-line synchronizer is not the best
choice for wide data paths, because a
variable delay line is needed for each
data bit separately
Delay-Line Synchronizer
Detection of an Unsafe Signal
 Received signal transition is unsafe, if it takes place within the keep-out region of the
receiver clock, i.e., within the aperture of the sampling flip-flop
 To detect this, the signal is sampled at the borders of the keep-out region: a flip-flop
setup time ts before and a flip-flop hold time th after the actual sampling edge of the
receiver clock
– if the results are different (XOR gate) the signal is unsafe
– otherwise the signal is safe
 Because the involved flip-flops may enter a metastable state, an appropriate time tw has
to be waited before the flag unsafe is updated
– in the mesochronous case we can wait a very long time, as it is done only once !
 Flag unsafe is then used to control the delay of the variable delay line
MUX
x
0 xd
1
tko
(= ts + th ) unsafe

x xd

Simple variable delay line

Two-Register Synchronizer
 In the delay-line synchronizer, we have a MUX
delay line and a flip-flop for each data bit
 In the two-register synchronizer, we have
only one delay line for the common
receiver clock but two flip-flops for each
data bit
– one flip-flop is operated with the
undelayed clock, the other with the
delayed clock (tko = length of the clock’s
keep-out region)
 We sample the signal with both flip-flops  Average delay of this device is
and pass the safe output forward tko
2
tcy
– unsafe = 0 => undelayed sample
tz   t dCQ  t dMUX 
tcy 2
– unsafe = 1 => delayed sample
where the first term is the keep-out
delay tko times the probability of the
lower flip-flop to be selected, tko /tcy
Two-Register Synchronizer
 FIFO Synchronizer
• A FIFO synchronizer uses a small ring buffer to decouple the transmitter and
receiver timing.
• A FIFO Synchronizer with a two element ring buffer is shown in figure.
• The transmit clock xclk is used to alternately sample the input signal x, into a pair
of flip flops.
• A toggle flip flop generates a transmit pointer, xp, that selects which flip flops clock
enable input.
• The output of the transmit flip flops are a pair of signal, x0 and xl, that are still
synchronized to the transmit clock but which change only every other cycle.
FIFO Synchronizer
FIFO Synchronizer
 FIFO synchronizer is built usually from
three sampling flip-flops per data bit (3-
MUX
place FIFO buffer)
0
– FIFO buffer is filled using the transmitter 1
clock xclk and the associated counter
which provides the transmit pointer xp 2
– FIFO buffer is emptied using the receiver
clock rclk and the associated counter
which provides the receive pointer rp
– receive pointer follows the transmit
pointer one step behind, i.e., when xp is
0,1,2 , rp is 2,0,1, respectively
 Each flip-flop output x0, x1, or x2 is
updated on every 3rd clock cycle and
passed to the MUX output xs as a clock-
cycle-wide sample during each 3-cycle  Hence, the 3-place FIFO synchronizer
round provides a stable and correct output as long
– this gives a clock-cycle-wide timing as the phase difference between xclk and
margin on both sides of each sample rclk is between – tcy and tcy
Plesiochronous Synchronization
 Receiver and transmitter clocks have slightly different frequencies
– for example, independent chrystal or local ring oscillators with the same nominal
frequency
 Basically, the same synchronizer types can be used as in mesochronous
synchronization
– delay line, two-register, FIFO
 However, now we have to resynchronize periodically, as the phase difference is
periodic and wraps every time it reaches 2
– for example, we may resynchronize once every 1000 receiver clock cycles
 We also need flow control to match data rates of the transmitter and receiver
even though the clock rates are different
– this ensures that we do not drop or replicate data at the receiver when the phase
difference wraps
 Plesiochronous FIFO Synchronizer
• A circuit composed of two flip flops and a multiplexer updates rp with a
synchronized version of xp whenever resync is asserted.
• The local clock is delayed by tx before sampling xp to assure that rp leads xp with
adequate margin at the point of transition. When resync is low, the top input of the
multiplexer is selected, and rp toggles.
• If resynch is simple tied high the circuit will update rp from xp on every cycle.
• In this case, rp will select the same transmitter flip flop for two cycles in succession
when xp slips by one cycle.
Plesiochronous FIFO Synchronizer

Plesichronous synchronizer with slower receiver

Plesiochronous FIFO Synchronizer

Plesichronous synchronizer with faster receiver

Plesiochronous FIFO Synchronizer
 Data is inserted into the FIFO buffer with
the transmitter clock xclk
 Data is removed from the FIFO buffer with
the receiver clock rclk
 Receive pointer rp is periodically updated
by synchronizing the transmit pointer xp to
the receiver clock rclk
– rp is replaced with the previous xp
whenever the control signal resync is high
– rp is incremented normally whenever
resync is low
– resync signal is driven by a controller
which is designed to activate a
resynchronization cycle whenever the
phase difference between xclk and rclk
wraps
 These updating events keep the counters in
resync
a correct phase, but lead to data dropping
or replication
Flow Control
 Whenever the phase difference between the  If the receiver is underrun, it inserts a
transmitter clock xclk and the receiver clock null symbol instead of duplicating a
rclk wraps, the transmitter data symbol after the resynchro-
– overruns the receiver, if xclk has a higher nization event
frequency than rclk  In the open-loop flow control, the
» a data symbol is dropped (lost) transmitter inserts nulls in the data
– underruns the receiver, if xclk has a lower stream with a frequency high enough to
frequency than rclk meet the maximum update latency
» a data symbol is replicated constraint on the receiver
 Data-rate mismatch problem is handled by – rate of actual data symbols in the
inserting null symbols into the data stream stream should be less than the clock
– extra signal — a presence bit frequency of the receiver
– reserved bit pattern  In the closed-loop flow control, the
 If the receiver is overrun, the resynchro- receiver requests a null symbol from
nization event is performed only when a null the transmitter when it is about to be
symbol is received overrun
– a null symbol is dropped, not a data symbol
General Periodic Synchronization
 Transmitter and receiver clocks are periodic, but there is no relationship
between the frequencies
– for example, independent chrystal or local ring oscillators with different nominal
frequencies
 In this case, a single synchronization will not be valid forever (meso-
chronous case) or even for a long time (plesiochronous case)
 However, we can still reduce the synchronizer delay by predicting when the
transmitter and receiver clocks will be in conflict
– flow control is needed as in plesiochronous synchronization
Clock Predictor
 Predicts the value of the transmitter clock, xclk, N
cycles trcy of the receiver clock, rclk, in the future
 This is the phase shift N (txcy–trcy) , where txcy is the
cycle time of the transmitter clock
 Such a phase shift can be generated using a simple
delay-locked loop

Predicted transmitter clock

(transmitter clock N receiver clock
cycles in the future)

N(txcy – trcy)
 Periodic Two-Register Synchronizer
 Waiting period must match the clock
MUX
prediction ―degree

– N-cycle waiting period for N-cycle prediction

– if N=1, doneWaiting is always high
– notice that waiting takes place in parallel with
receiving data
» no extra delay introduced
rclk
pxclk
Clock
xclk Predictor

rclk

rclk
General Purpose Asynchronous FIFO Synchronizer
 Data in inserted into the FIFO buffer with the transmitter clock xclk keeping the control
signal shiftIn high
 Data in removed from the FIFO buffer with the receiver clock rclk keeping the control
signal shiftOut high
 No actual synchronization delay or failures in the data path
 Provides inherent flow control via the full and empty signals
– when the FIFO is about to be overrun, full is asserted, and the transmitter pauses its data
sending process by setting shiftIn low
– when the FIFO is about to be underrun, empty is asserted, and the receiver pauses reading by
setting shiftOut low
shiftOut
Read ptr
Brute-force rclk
full sync
Compare
sx
FIFO
x
Compare
Brute-force empty
sync
xclk
Write ptr
shiftIn
Thank You