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Mohamed Mohsen CV

Mohamed Mohsen Kamal Mousa is a recent Electronics and Communications Engineering graduate from Cairo University, with a strong focus on Digital IC Design and Design Verification. He has completed a notable graduation project on the Digital Verification of CXL link layer using UVM and has gained practical experience through various training programs and projects in digital design and verification. His skills include System Verilog, UVM, and Verilog, along with experience in machine learning and communication projects.

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17 views2 pages

Mohamed Mohsen CV

Mohamed Mohsen Kamal Mousa is a recent Electronics and Communications Engineering graduate from Cairo University, with a strong focus on Digital IC Design and Design Verification. He has completed a notable graduation project on the Digital Verification of CXL link layer using UVM and has gained practical experience through various training programs and projects in digital design and verification. His skills include System Verilog, UVM, and Verilog, along with experience in machine learning and communication projects.

Uploaded by

Hamada
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Mohamed Mohsen Kamal Mousa

Giza, Hadaek el Ahram | +201122352287 | Military status: Exempted


mohamed.mohsen.km@gmail.com | https://www.linkedin.com/in/mohamed-mohsen-543b2b220/

SUMMARY

A recent graduate with a Bachelor's degree in Electronics and Communications Engineering from Cairo
University, passionate about Digital IC Design and Design Verification. Eager to apply technical skills
and contribute positively to a collaborative engineering environment.

EDUCATION

➢ Cairo University - Faculty of Engineering - Electronics & Communication department

➢ Graduation year: 2024

➢ Cumulative grade: Very Good with Honors (82%)

GRADUATION PROJECT

➢ Digital Verification of CXL link layer using UVM, Sponsored by (Si-Vision).


➢ Grade: Excellent
Project phases:
- Understanding the specifications of the CXL link layer.
- Reviewing the RTL design of the link layer retry module and using white-box technique for verification.
- Developing a comprehensive verification plan outlining the features to be tested.
- Creating various test scenarios and covering them using SystemVerilog Assertions.
- Finding some bugs in the state transitions and a critical counter.
- Achieving 100% functional coverage for the verified module.

EXPERIENCE
➢ Si-Vision Academy (Digital Verification program) Dec 2024 - May 2025
Content: -
- System Verilog concepts. - Hierarchical testbenches
- OOP - UVM
- Transaction Level Modeling - Virtual sequences & sequencer

➢ CND Electronics Training (Digital IC Design and Verification Track) Sep 2023 - May 2024
Content for digital IC design: -
- Verilog modeling & synthesis. - Design For Testing.
- Timing analysis & constraints. - Formality.

➢ Digital IC Design Diploma Jul 2023 - Oct 2023

➢ Full Embedded Systems Diploma Jul 2022 - Oct 2022


PROJECTS

➢ Verification projects using UVM:


- Verification of AES. - Verification of memory.
- Verification of a small computation - Verification of ALU.
storage.

➢ Design projects:
- RTL to GDS Implementation of Low Power - Design of UART (TX & RX).
Configurable Multi Clock Digital System.
- Design of FFE equalizer. - Design of Register file.
- Design of a small computation storage. - Design of ALU.

➢ Machine learning projects:


- Optimized SVM Classification for Reduced MNIST with Augmentation and Semi-Supervised
Learning.
- Data Augmentation Pipeline for Improved MNIST Digit Classification Using LeNet.
➢ Communication projects:
- BER Performance Analysis of BPSK with Channel Coding Using Hamming Code.
- Single Carrier System with QPSK/16-QAM over Frequency-Selective Fading Channel.

SKILLS
➢ Design Verification:
- System Verilog. - UVM.
- Functional coverage. - SVA.
➢ Digital Design:
- Verilog. - TCL.
- Synthesis. - DFT.

➢ Tools:
- VCS - Quartus.
- QuestaSim. - Cadence Virtuoso.
- ModelSim. - Visual Studio.

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