6 Digital Logic (292)

Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer
arithmetic (fixed and floating point)

6.1 Adder (9)

6.1.1 Adder: GATE CSE 1988 | Question: 4ii

Using binary full adders and other logic gates (if necessary), design an adder for adding -bit number
(including sign) in complement notation.

gate1988 digital-logic descriptive adder

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6.1.2 Adder: GATE CSE 1990 | Question: 1-i

Fill in the blanks:

In the two bit full-adder/subtractor unit shown in below figure, when the switch is in position ___________
using _________ arithmetic.

gate1990 digital-logic adder fill-in-the-blanks

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6.1.3 Adder: GATE CSE 1997 | Question: 2.5

An N-bit carry lookahead adder, where is a multiple of , employs ICs ( bit ALU) and (
bit carry lookahead generator).
The minimum addition time using the best architecture for this adder is

A. proportional to B. proportional to
C. a constant D. None of the above
gate1997 digital-logic normal adder

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6.1.4 Adder: GATE CSE 1999 | Question: 2.16

The number of full and half-adders required to add -bit numbers is

A. half-adders, full-adders B. half-adder, full-adders

C. half-adders, full-adders D. half-adders, full-adders
gate1999 digital-logic normal adder
 Answer key☟

6.1.5 Adder: GATE CSE 2003 | Question: 46

Consider the ALU shown below.

If the operands are in complement representation, which of the following operations can be performed by
suitably setting the control lines and only (+ and – denote addition and subtraction respectively)?

A. , and , but not B. , and , but not

C. , but not or D. , and , and
gatecse-2003 digital-logic normal adder

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6.1.6 Adder: GATE CSE 2004 | Question: 62

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND,
NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented
forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that
the carry network has been implemented using two-level AND-OR logic.

A. 4 time units B. 6 time units

C. 10 time units D. 12 time units
gatecse-2004 digital-logic normal adder

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6.1.7 Adder: GATE CSE 2015 Set 2 | Question: 48

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and
one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation
delay of an AND/OR gate is microseconds. A -bit-ripple-carry binary adder is implemented by using four full
adders. The total propagation time of this -bit binary adder in microseconds is ______.

gatecse-2015-set2 digital-logic adder normal numerical-answers

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6.1.8 Adder: GATE CSE 2016 Set 1 | Question: 33

Consider a carry look ahead adder for adding two -bit integers, built using gates of fan-in at most two. The
time to perform addition using this adder is

A. B.
C. D. )
gatecse-2016-set1 digital-logic adder normal

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6.1.9 Adder: GATE CSE 2016 Set 2 | Question: 07

Consider an eight-bit ripple-carry adder for computing the sum of and , where and are integers
represented in 's complement form. If the decimal value of is one, the decimal value of that leads to
the longest latency for the sum to stabilize is ___________
 gatecse-2016-set2 digital-logic adder normal numerical-answers

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6.2 Array Multiplier (2)

6.2.1 Array Multiplier: GATE CSE 1999 | Question: 1.21

The maximum gate delay for any output to appear in an array multiplier for multiplying two bit numbers is

A. B. C. D.
gate1999 digital-logic normal array-multiplier

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6.2.2 Array Multiplier: GATE CSE 2003 | Question: 11

Consider an array multiplier for multiplying two bit numbers. If each gate in the circuit has a unit delay, the
total delay of the multiplier is

A. B. C. D.
gatecse-2003 digital-logic normal array-multiplier

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6.3 Boolean Algebra (32)

6.3.1 Boolean Algebra: GATE CSE 1987 | Question: 1-II

The total number of Boolean functions which can be realised with four variables is:

A. B. C. D.
gate1987 digital-logic boolean-algebra functions combinatory

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6.3.2 Boolean Algebra: GATE CSE 1987 | Question: 12-a

The Boolean expression is equivalent to

A. B.
C. D.
gate1987 digital-logic boolean-algebra easy

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6.3.3 Boolean Algebra: GATE CSE 1988 | Question: 2-iii

Let be defined as a Boolean operation given as and let . If then

prove that .

gate1988 digital-logic descriptive boolean-algebra

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6.3.4 Boolean Algebra: GATE CSE 1989 | Question: 4-x

A switching function is said to be neutral if the number of input combinations for which its value is is equal
to the number of input combinations for which its value is Compute the number of neutral switching
functions of variables (for a given ).

gate1989 descriptive digital-logic boolean-algebra

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6.3.5 Boolean Algebra: GATE CSE 1989 | Question: 5-a

Find values of Boolean variables which satisfy the following equations:

A+ B = 1
AC = BC
A+C=1
AB = 0

gate1989 descriptive digital-logic boolean-algebra

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6.3.6 Boolean Algebra: GATE CSE 1992 | Question: 02-i

The operation which is commutative but not associative is:

A. AND B. OR C. EX-OR D. NAND

gate1992 easy digital-logic boolean-algebra multiple-selects

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6.3.7 Boolean Algebra: GATE CSE 1994 | Question: 4

A. L e t be a Boolean operation defined as . If then evaluate and fill in the

blanks:
i. ______
ii. ______
B. Solve the following boolean equations for the values of and

gate1994 digital-logic normal boolean-algebra descriptive

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6.3.8 Boolean Algebra: GATE CSE 1995 | Question: 2.5

What values of and satisfy the following simultaneous Boolean equations?

A. B.
C. D.
gate1995 digital-logic boolean-algebra easy

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6.3.9 Boolean Algebra: GATE CSE 1997 | Question: 2-1

Let be defined as . Let . Value of is

A. B. C. D.
gate1997 digital-logic normal boolean-algebra

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6.3.10 Boolean Algebra: GATE CSE 1998 | Question: 1.13

What happens when a bit-string is XORed with itself -times as shown:

A. complements when is even B. complements when is odd

 C. divides by always D. remains unchanged when is even
gate1998 digital-logic normal boolean-algebra

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6.3.11 Boolean Algebra: GATE CSE 1998 | Question: 2.8

Which of the following operations is commutative but not associative?

A. AND B. OR C. NAND D. EXOR

gate1998 digital-logic easy boolean-algebra

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6.3.12 Boolean Algebra: GATE CSE 1999 | Question: 1.7

Which of the following expressions is not equivalent to ?

A. B. C. D.
gate1999 digital-logic easy boolean-algebra

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6.3.13 Boolean Algebra: GATE CSE 2000 | Question: 2.10

The simultaneous equations on the Boolean variables and ,

have the following solution for and respectively:

A. B.
C. D.
gatecse-2000 digital-logic boolean-algebra easy

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6.3.14 Boolean Algebra: GATE CSE 2002 | Question: 2-3

Let . Simplified expression for function is

A. B. C. D. None of the above

gatecse-2002 digital-logic boolean-algebra normal

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6.3.15 Boolean Algebra: GATE CSE 2004 | Question: 17

A Boolean function is equivalent to

A. B. C. D.
gatecse-2004 digital-logic easy boolean-algebra

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6.3.16 Boolean Algebra: GATE CSE 2007 | Question: 32

Let . Which of the following expressions are NOT equivalent to

?
P:
Q:
R:
S:

A. P only B. Q and S C. R and S D. S only

gatecse-2007 digital-logic normal boolean-algebra

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6.3.17 Boolean Algebra: GATE CSE 2007 | Question: 33

Define the connective for the Boolean variables and as:

Let . Consider the following expressions , and .

Which of the following is TRUE?

A. Only and are valid. B. Only and are valid.

C. Only and are valid. D. All , , are valid.
gatecse-2007 digital-logic normal boolean-algebra

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6.3.18 Boolean Algebra: GATE CSE 2008 | Question: 26

If are Boolean variables, then

simplifies to

A. B. C. D.

gatecse-2008 easy digital-logic boolean-algebra

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6.3.19 Boolean Algebra: GATE CSE 2012 | Question: 6

The truth table represents the Boolean function

A. B. C. D.
gatecse-2012 digital-logic easy boolean-algebra

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6.3.20 Boolean Algebra: GATE CSE 2013 | Question: 21

Which one of the following expressions does NOT represent exclusive NOR of and ?

A. B.
C. D.
gatecse-2013 digital-logic easy boolean-algebra

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6.3.21 Boolean Algebra: GATE CSE 2014 Set 2 | Question: 6

The dual of a Boolean function , written as is the same expression as that of

with and swapped. is said to be self-dual if . The number of self-dual functions with
Boolean variables is

A. B. C. D.
gatecse-2014-set2 digital-logic normal dual-function boolean-algebra

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6.3.22 Boolean Algebra: GATE CSE 2014 Set 3 | Question: 55

Let denote the exclusive OR (XOR) operation. Let ' ' and ' ' denote the binary constants. Consider the
following Boolean expression for over two variables and :

The equivalent expression for is

A. B.
C. D.
gatecse-2014-set3 digital-logic normal boolean-algebra

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6.3.23 Boolean Algebra: GATE CSE 2015 Set 2 | Question: 37

The number of min-terms after minimizing the following Boolean expression is _______.

gatecse-2015-set2 digital-logic boolean-algebra normal numerical-answers

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6.3.24 Boolean Algebra: GATE CSE 2016 Set 1 | Question: 06

Consider the Boolean operator # with the following properties :

and Then is equivalent to

A. B.
C. D.
gatecse-2016-set1 digital-logic boolean-algebra easy

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6.3.25 Boolean Algebra: GATE CSE 2016 Set 2 | Question: 08

Let, where are Boolean variables, and is the XOR operator.

Which one of the following must always be TRUE?

A.
B.
C.
D.

gatecse-2016-set2 digital-logic boolean-algebra normal

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6.3.26 Boolean Algebra: GATE CSE 2017 Set 2 | Question: 27

If are Boolean variables, then which one of the following is INCORRECT?

 A. B.
C. D.
gatecse-2017-set2 digital-logic boolean-algebra normal

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6.3.27 Boolean Algebra: GATE CSE 2018 | Question: 4

Let and denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the
following is NOT CORRECT?

A.
B.
C.
D.

gatecse-2018 digital-logic normal boolean-algebra 1-mark

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6.3.28 Boolean Algebra: GATE CSE 2019 | Question: 6

Which one of the following is NOT a valid identity?

A. B.
C. D.
gatecse-2019 digital-logic boolean-algebra 1-mark

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6.3.29 Boolean Algebra: GATE CSE 2021 Set 1 | Question: 42

Consider the following Boolean expression.

Which of the following Boolean expressions is/are equivalent to (complement of )?

A.
B.
C.
D.

gatecse-2021-set1 multiple-selects digital-logic boolean-algebra 2-marks

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6.3.30 Boolean Algebra: GATE CSE 2024 | Set 2 | Question: 20

​For a Boolean variable , which of the following statements is/are FALSE?

A. B. C. D.
gatecse2024-set2 digital-logic boolean-algebra easy multiple-selects

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6.3.31 Boolean Algebra: GATE IT 2004 | Question: 44

The function is equivalent to

A. B.
C. D.
gateit-2004 digital-logic boolean-algebra easy
 Answer key☟

6.3.32 Boolean Algebra: GATE IT 2005 | Question: 7

Which of the following expressions is equivalent to

A. B.
C. D. None of these
gateit-2005 digital-logic normal boolean-algebra

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6.4 Booths Algorithm (6)

6.4.1 Booths Algorithm: GATE CSE 1990 | Question: 8b

State the Booth's algorithm for multiplication of two numbers. Draw a block diagram for the implementation
of the Booth's algorithm for determining the product of two -bit signed numbers.

gate1990 descriptive digital-logic booths-algorithm

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6.4.2 Booths Algorithm: GATE CSE 1996 | Question: 1.23

Booth’s algorithm for integer multiplication gives worst performance when the multiplier pattern is

A. B.
C. D.
gate1996 digital-logic booths-algorithm normal

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6.4.3 Booths Algorithm: GATE CSE 1999 | Question: 1.20

Booth's coding in bits for the decimal number is:

A. B. C. D.
gate1999 digital-logic number-representation booths-algorithm normal

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6.4.4 Booths Algorithm: GATE IT 2005 | Question: 8

Using Booth's Algorithm for multiplication, the multiplier will be recoded as

A. - - B.
C. - D. -
gateit-2005 digital-logic booths-algorithm normal

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6.4.5 Booths Algorithm: GATE IT 2006 | Question: 38

When multiplicand is multiplied by multiplier using bit-pair recoding in Booth's

algorithm, partial products are generated according to the following table.
 The partial products for rows and are

A. and B. and C. and D. and

gateit-2006 digital-logic booths-algorithm difficult

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6.4.6 Booths Algorithm: GATE IT 2008 | Question: 42

The two numbers given below are multiplied using the Booth's algorithm.
Multiplicand :
Multiplier:
How many additions/Subtractions are required for the multiplication of the above two numbers?

A. B. C. D.
gateit-2008 digital-logic booths-algorithm normal

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6.5 Canonical Normal Form (9)

6.5.1 Canonical Normal Form: GATE CSE 2002 | Question: 2-1

Consider the following logic circuit whose inputs are functions and output is

Given that

and

is

A. B.
C. D. None of the above
gatecse-2002 digital-logic normal canonical-normal-form circuit-output

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6.5.2 Canonical Normal Form: GATE CSE 2007 | Question: 48

Which of the following is TRUE about formulae in Conjunctive Normal Form?

A. For any formula, there is a truth assignment for which at least half the clauses evaluate to true.
B. For any formula, there is a truth assignment for which all the clauses evaluate to true.
C. There is a formula such that for each truth assignment, at most one-fourth of the clauses evaluate to true.
D. None of the above.

gatecse-2007 digital-logic normal conjunctive-normal-form canonical-normal-form

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6.5.3 Canonical Normal Form: GATE CSE 2008 | Question: 8

Given , and in canonical sum of products form (in decimal) for the circuit

then is

A. B.
C. D.
gatecse-2008 digital-logic canonical-normal-form easy

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6.5.4 Canonical Normal Form: GATE CSE 2010 | Question: 6

The minterm expansion of is

A. B.
C. D.
gatecse-2010 digital-logic canonical-normal-form normal

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6.5.5 Canonical Normal Form: GATE CSE 2015 Set 3 | Question: 43

The total number of prime implicants of the function is __________

gatecse-2015-set3 digital-logic canonical-normal-form normal numerical-answers

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6.5.6 Canonical Normal Form: GATE CSE 2015 Set 3 | Question: 44

Given the function , where is a function in three Boolean variables and and
, consider the following statements.

Which of the following is true?

A. (S1)-False, (S2)-True, (S3)-True, (S4)-False

B. (S1)-True, (S2)-False, (S3)-False, (S4)-True
C. (S1)-False, (S2)-False, (S3)-True, (S4)-True
D. (S1)-True, (S2)-True, (S3)-False, (S4)-False

gatecse-2015-set3 digital-logic canonical-normal-form normal

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 6.5.7 Canonical Normal Form: GATE CSE 2019 | Question: 50

What is the minimum number of -input NOR gates required to implement a -variable function expressed
in sum-of-minterms form as Assume that all the inputs and their
complements are available. Answer: _______

gatecse-2019 numerical-answers digital-logic canonical-normal-form 2-marks

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6.5.8 Canonical Normal Form: GATE CSE 2020 | Question: 28

Consider the Boolean function .

Which one of the following minterm lists represents the circuit given above?

A. B.
C. D.
gatecse-2020 digital-logic canonical-normal-form 2-marks

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6.5.9 Canonical Normal Form: GATE CSE 2024 | Set 2 | Question: 40

Consider -variable functions expressed in sum-of-minterms form as given below.

With respect to the circuit given above, which of the following options is/are CORRECT?

A. B.
C. D.
gatecse2024-set2 digital-logic canonical-normal-form multiple-selects

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6.6 Carry Generator (2)

6.6.1 Carry Generator: GATE CSE 2006 | Question: 36

Given two three bit numbers and and the carry in, the function that represents
the carry generate function when these two numbers are added is:

A.
B.
C.
D.
 gatecse-2006 digital-logic normal carry-generator adder

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6.6.2 Carry Generator: GATE CSE 2007 | Question: 35

In a look-ahead carry generator, the carry generate function and the carry propagate function for
inputs and are given by:

The expressions for the sum bit and the carry bit of the look ahead carry adder are given by:

Consider a two-level logic implementation of the look-ahead carry generator. Assume that all and are
available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The
number of AND gates and OR gates needed to implement the look-ahead carry generator for a -bit adder with
and as its outputs are respectively:

A. B. C. D.
gatecse-2007 digital-logic normal carry-generator adder

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6.7 Circuit Output (39)

6.7.1 Circuit Output: GATE CSE 1987 | Question: 1-IV

The output of the below multiplexer circuit can be represented by

A. B.
C. D.
gate1987 digital-logic combinational-circuit multiplexer circuit-output

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6.7.2 Circuit Output: GATE CSE 1989 | Question: 4-ix

Explain the behaviour of the following logic circuit with level input and output .

gate1989 descriptive digital-logic circuit-output

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6.7.3 Circuit Output: GATE CSE 1990 | Question: 3-i

Choose the correct alternatives (More than one may be correct).

Two NAND gates having open collector outputs are tied together as shown in below figure.

The logic function implemented by the circuit is,

A. B.
C. D.
gate1990 normal digital-logic circuit-output

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6.7.4 Circuit Output: GATE CSE 1991 | Question: 5-a

Analyse the circuit in Fig below and complete the following table

gate1991 digital-logic normal circuit-output sequential-circuit descriptive

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6.7.5 Circuit Output: GATE CSE 1993 | Question: 19

A control algorithm is implemented by the NAND – gate circuitry given in figure below, where and are
state variable implemented by flip-flops, and is control input. Develop the state transition table for this
controller.
 gate1993 digital-logic sequential-circuit flip-flop circuit-output normal descriptive

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6.7.6 Circuit Output: GATE CSE 1993 | Question: 6-3

For the initial state of , the function performed by the arrangement of the flip-flops in figure is:

A. Shift Register B. Counter

C. Counter D. Counter
E. None of the above
gate1993 digital-logic sequential-circuit flip-flop digital-counter circuit-output multiple-selects

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6.7.7 Circuit Output: GATE CSE 1993 | Question: 6.1

Identify the logic function performed by the circuit shown in figure.

A. exclusive OR B. exclusive NOR C. NAND D. NOR

E. None of the above

gate1993 digital-logic combinational-circuit circuit-output normal

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6.7.8 Circuit Output: GATE CSE 1993 | Question: 6.2

If the state machine described in figure should have a stable state, the restriction on the inputs is given by

A. B.
C. D.
E.
gate1993 digital-logic normal circuit-output sequential-circuit

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6.7.9 Circuit Output: GATE CSE 1994 | Question: 1.8

The logic expression for the output of the circuit shown in figure below is:
 A. B.

C. D.
gate1994 digital-logic circuit-output normal

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6.7.10 Circuit Output: GATE CSE 1994 | Question: 11

Find the contents of the flip-flop and in the circuit of figure, after giving four clock pulses to the
clock terminal. Assume initially.

gate1994 digital-logic sequential-circuit digital-counter circuit-output normal descriptive

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6.7.11 Circuit Output: GATE CSE 1996 | Question: 2.21

Consider the circuit in below figure which has a four bit binary number as input and a five bit binary
number, as output.

A. Binary to Hex conversion B. Binary to BCD conversion

C. Binary to Gray code conversion D. Binary to conversion
gate1996 digital-logic circuit-output normal

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6.7.12 Circuit Output: GATE CSE 1996 | Question: 2.22

Consider the circuit in figure. implements

 A. B.

C. D.
gate1996 digital-logic circuit-output easy multiplexer

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6.7.13 Circuit Output: GATE CSE 1996 | Question: 24-a

Consider the synchronous sequential circuit in the below figure

Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to
the values of flip-flops as given below.

gate1996 digital-logic circuit-output normal descriptive

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6.7.14 Circuit Output: GATE CSE 1996 | Question: 24-b

Consider the synchronous sequential circuit in the below figure

Given that the initial state of the circuit is identify the set of states, which are not reachable.

gate1996 normal digital-logic circuit-output descriptive

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6.7.15 Circuit Output: GATE CSE 1997 | Question: 5.5

Consider a logic circuit shown in figure below. The functions (in canonical sum of products
form in decimal notation) are :

The function is

A. B. C. D.

gate1997 digital-logic circuit-output normal

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6.7.16 Circuit Output: GATE CSE 1999 | Question: 2.8

Consider the circuit shown below. In a certain steady state, the line is at . What are the possible values
of and in this state?

A. B.
C. D.
gate1999 digital-logic circuit-output normal

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6.7.17 Circuit Output: GATE CSE 2000 | Question: 2.12

The following arrangement of master-slave flip flops

has the initial state of as (respectively). After three clock cycles the output state is (respectively),

A. B. C. D.
gatecse-2000 digital-logic circuit-output normal flip-flop

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6.7.18 Circuit Output: GATE CSE 2001 | Question: 2.8

Consider the following circuit with initial state . The D Flip-flops are positive edged triggered
and have set up times 20 nanosecond and hold times
Consider the following timing diagrams of X and C. The clock period of nanosecond. Which one is the
correct plot of Y?

A.

B.

C.

D.

gatecse-2001 digital-logic circuit-output normal

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6.7.19 Circuit Output: GATE CSE 2002 | Question: 2.2

Consider the following multiplexer where are four data input lines selected by two address
line combinations respectively and is the output of the multiplexor. EN is the
Enable input.

The function implemented by the above circuit is

A. B. C. D. None of the above

gatecse-2002 digital-logic circuit-output normal

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6.7.20 Circuit Output: GATE CSE 2004 | Question: 61

Consider the partial implementation of a counter using flip-flops following the sequence
as shown below.
To complete the circuit, the input should be

A. B. C. D.
gatecse-2004 digital-logic circuit-output normal

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6.7.21 Circuit Output: GATE CSE 2005 | Question: 15

Consider the following circuit.

Which one of the following is TRUE?

A. is independent of B. is independent of
C. is independent of D. None of is redundant
gatecse-2005 digital-logic circuit-output normal

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6.7.22 Circuit Output: GATE CSE 2005 | Question: 62

Consider the following circuit involving a positive edge triggered D FF.

Consider the following timing diagram. Let represents the logic level on the line in the -th clock period.

Let represent the complement of . The correct output sequence on over the clock periods through is:

A. B.
C. D.
gatecse-2005 digital-logic circuit-output normal

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6.7.23 Circuit Output: GATE CSE 2005 | Question: 64

Consider the following circuit:

The flip-flops are positive edge triggered s. Each state is designated as a two-bit string . Let the initial
state be The state transition sequence is

A. C. D.
B.
gatecse-2005 digital-logic circuit-output

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6.7.24 Circuit Output: GATE CSE 2006 | Question: 35

Consider the circuit above. Which one of the following options correctly represents

A. B.
C. D.
gatecse-2006 digital-logic circuit-output normal

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6.7.25 Circuit Output: GATE CSE 2006 | Question: 37

Consider the circuit in the diagram. The operator represents Ex-OR. The D flip-flops are initialized to
zeroes (cleared).

The following data: is supplied to the “data” terminal in nine clock cycles. After that the values of
are:

A. B. C. D.
gatecse-2006 digital-logic circuit-output easy

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6.7.26 Circuit Output: GATE CSE 2006 | Question: 8

You are given a free running clock with a duty cycle of and a digital waveform which changes only at
the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the
phase of by ?

A.

B.

C.

D.

gatecse-2006 digital-logic normal circuit-output

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6.7.27 Circuit Output: GATE CSE 2007 | Question: 36

The control signal functions of a - binary counter are given below (where is “don’t care”):

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at then it cycles through the
following sequence:

A. B. C. D.
gatecse-2007 digital-logic circuit-output normal

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6.7.28 Circuit Output: GATE CSE 2010 | Question: 31

What is the boolean expression for the output of the combinational logic circuit of NOR gates given below?
 A. B.
C. D.
gatecse-2010 digital-logic circuit-output normal

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6.7.29 Circuit Output: GATE CSE 2010 | Question: 32

In the sequential circuit shown below, if the initial value of the output is . What are the next four
values of ?

A. , , , B. , , ,
C. , , , D. , , ,
gatecse-2010 digital-logic circuit-output normal

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6.7.30 Circuit Output: GATE CSE 2010 | Question: 9

The Boolean expression of the output of the multiplexer shown below is

A. B.
C. D.
gatecse-2010 digital-logic circuit-output easy

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6.7.31 Circuit Output: GATE CSE 2011 | Question: 50

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, and have a value , and respectively,
what shall be the value of after the clock edge?

A. B. C. D.
gatecse-2011 digital-logic circuit-output flip-flop normal

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6.7.32 Circuit Output: GATE CSE 2011 | Question: 51

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

If all the flip-flops were reset to at power on, what is the total number of distinct outputs (states) represented by
generated by the counter?

A. B. C. D.
gatecse-2011 digital-logic circuit-output normal

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6.7.33 Circuit Output: GATE CSE 2014 Set 3 | Question: 45

The above synchronous sequential circuit built using JK flip-flops is initialized with . The state
sequence for this circuit for the next clock cycles is
 A. B.
C. D.
gatecse-2014-set3 digital-logic circuit-output normal

Answer key☟

6.7.34 Circuit Output: GATE IT 2005 | Question: 10

A two-way switch has three terminals and In ON position (logic value ), is connected to and in
OFF position, is connected to . Two of these two-way switches and are connected to a bulb as
shown below.

Which of the following expressions, if true, will always result in the lighting of the bulb ?

A. B.

C. D.
gateit-2005 digital-logic circuit-output normal

Answer key☟

6.7.35 Circuit Output: GATE IT 2005 | Question: 43

Which of the following input sequences will always generate a at the output at the end of the third cycle?

A. B. C. D.

gateit-2005 digital-logic circuit-output normal

Answer key☟

6.7.36 Circuit Output: GATE IT 2006 | Question: 36

The majority function is a Boolean function that takes the value whenever a majority of the
variables are In the circuit diagram for the majority function shown below, the logic gates for the
boxes labeled and are, respectively,
 A. B. C. D.
gateit-2006 digital-logic circuit-output normal

Answer key☟

6.7.37 Circuit Output: GATE IT 2007 | Question: 38

The following expression was to be realized using -input AND and OR gates. However, during the
fabrication all -input AND gates were mistakenly substituted by -input NAND gates.

What is the function finally realized ?

A. B.
C. D.
gateit-2007 digital-logic circuit-output normal

Answer key☟

6.7.38 Circuit Output: GATE IT 2007 | Question: 40

What is the final value stored in the linear feedback shift register if the input is ?

A. B. C. D.
gateit-2007 digital-logic circuit-output normal

Answer key☟

6.7.39 Circuit Output: GATE IT 2007 | Question: 45

The line in the following figure is permanently connected to the ground.

Which of the following inputs will detect the fault ?

A. B. C. D. None of these
gateit-2007 digital-logic circuit-output normal

Answer key☟

6.8 Combinational Circuit (2)

 6.8.1 Combinational Circuit: GATE CSE 2022 | Question: 30

Consider a digital display system shown in the figure that displays the contents of register A
code word is used to load a word in either from or from is a word memory
segment and is a word register file. Based on the value of mode bit selects an input word to load in
and interface with the corresponding bits in the code word to choose the addressed word. Which one of the
following represents the functionality of and

A. is multiplexer is multiplexer is multiplexer

B. is decoder is decoder is encoder
C. is decoder is decoder is multiplexer
D. is de-multiplexer is de-multiplexer is multiplexer

gatecse-2022 digital-logic combinational-circuit 2-marks

Answer key☟

6.8.2 Combinational Circuit: GATE CSE 2024 | Set 1 | Question: 18

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal
transitions occur instantaneously and that wires have no delays. Which of the following statements about the
circuit is/are CORRECT?

A. With no propagation delays, the output is always logic Zero

B. With no propagation delays, the output is always logic One
C. With propagation delays, the output can have a transient logic One after transitions from logic Zero to logic
One
D. With propagation delays, the output can have a transient logic Zero after transitions from logic One to logic
Zero

gatecse2024-set1 multiple-selects digital-logic combinational-circuit

Answer key☟

6.9 Decoder (3)

6.9.1 Decoder: GATE CSE 2007 | Question: 8, ISRO2011-31

How many -to- line decoders with an enable input are needed to construct a -to- line decoder without
using any other logic gates?
 A. B. C. D.
gatecse-2007 digital-logic normal isro2011 decoder

Answer key☟

6.9.2 Decoder: GATE CSE 2020 | Question: 20

If there are input lines and output lines for a decoder that is used to uniquely address a byte
addressable KB RAM, then the minimum value of is ________ .

gatecse-2020 numerical-answers digital-logic decoder 1-mark

Answer key☟

6.9.3 Decoder: GATE IT 2008 | Question: 9

What Boolean function does the circuit below realize?

A. B.
C. D.
gateit-2008 digital-logic circuit-output decoder normal

Answer key☟

6.10 Digital Circuits (6)

6.10.1 Digital Circuits: GATE CSE 1996 | Question: 5

A logic network has two data inputs and , and two control inputs and . It implements the function
according to the following table.

Implement the circuit using one to Multiplexer, one input Exclusive OR gate, one input AND gate, one
input OR gate and one Inverter.

gate1996 digital-logic normal digital-circuits descriptive

Answer key☟

6.10.2 Digital Circuits: GATE CSE 2002 | Question: 7

A. Express the function with only one complement operation and one or more AND/OR
operations. Draw the logic circuit implementing the expression obtained, using a single NOT gate and one or
more AND/OR gates.
B. Transform the following logic circuit (without expressing its switching function) into an equivalent logic circuit
that employs only NAND gates each with -inputs.
 gatecse-2002 digital-logic normal descriptive digital-circuits

Answer key☟

6.10.3 Digital Circuits: GATE CSE 2003 | Question: 47

Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays and as shown in the figure. Both XOR gates and all
wires have zero delays. Assume that all gate inputs, outputs, and wires are stable at logic level at time . If the
following waveform is applied at input , how many transition(s) (change of logic levels) occur(s) at during the
interval from to ns?

A. B. C. D.
gatecse-2003 digital-logic digital-circuits

Answer key☟

6.10.4 Digital Circuits: GATE CSE 2011 | Question: 13

Which one of the following circuits is NOT equivalent to a -input (exclusive ) gate?

A.

B.

C.

D.

gatecse-2011 digital-logic normal digital-circuits

Answer key☟

6.10.5 Digital Circuits: GATE CSE 2013 | Question: 5

In the following truth table, if and only if the input is valid.

 What function does the truth table represent?

A. Priority encoder B. Decoder

C. Multiplexer D. Demultiplexer
gatecse-2013 digital-logic normal digital-circuits

Answer key☟

6.10.6 Digital Circuits: GATE CSE 2014 Set 3 | Question: 8

Consider the following combinational function block involving four Boolean variables where
are inputs and is the output.
f(x, a, b, y)
{
if(x is 1) y = a;
else y = b;
}

Which one of the following digital logic blocks is the most suitable for implementing this function?

A. Full adder B. Priority encoder C. Multiplexor D. Flip-flop

gatecse-2014-set3 digital-logic easy digital-circuits

Answer key☟

6.11 Digital Counter (17)

6.11.1 Digital Counter: GATE CSE 1987 | Question: 1-III

The above circuit produces the output sequence:

A. B.
C. D.
gate1987 digital-logic sequential-circuit flip-flop digital-counter

Answer key☟

6.11.2 Digital Counter: GATE CSE 1987 | Question: 10c

Give a minimal DFA that performs as a 's counter, i.e. outputs a each time the number of
's in the input sequence is a multiple of .

gate1987 digital-logic digital-counter descriptive

Answer key☟
6.11.3 Digital Counter: GATE CSE 1990 | Question: 5-c

For the synchronous counter shown in Fig write the truth table of , and after each pulse,
starting from and determine the counting sequence and also the modulus of the
counter.

gate1990 descriptive digital-logic sequential-circuit flip-flop digital-counter

Answer key☟

6.11.4 Digital Counter: GATE CSE 1991 | Question: 5-c

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that
the propagation delay through each flip flop and each AND gate is . Also, assume that the setup time
for the inputs of the flip flops is negligible.

gate1991 digital-logic sequential-circuit flip-flop digital-counter

Answer key☟

6.11.5 Digital Counter: GATE CSE 1994 | Question: 2-1

The number of flip-flops required to construct a binary modulo counter is __________

gate1994 digital-logic sequential-circuit flip-flop digital-counter fill-in-the-blanks

Answer key☟

6.11.6 Digital Counter: GATE CSE 2002 | Question: 8

Consider the following circuit. and are three bit binary numbers input to the circuit.
The output is . R0, R1 and R2 are registers with loading clock shown. The registers are
loaded with their input data with the falling edge of a clock pulse (signal CLOCK shown) and appears as shown.
The bits of input number A, B and the full adders are as shown in the circuit. Assume Clock period is greater than
the settling time of all circuits.
a. For 8 clock pulses on the CLOCK terminal and the inputs as shown, obtain the output (sequence of
values of Assume initial contents of and as all zeros.

b. What does the circuit implement?

gatecse-2002 digital-logic normal descriptive digital-counter

Answer key☟

6.11.7 Digital Counter: GATE CSE 2011 | Question: 15

The minimum number of flip-flops needed to design a mod-258 counter is

A. 9 B. 8 C. 512 D. 258
gatecse-2011 digital-logic normal digital-counter

Answer key☟

6.11.8 Digital Counter: GATE CSE 2014 Set 2 | Question: 7

Let . A circuit is built by giving the output of an -bit binary counter as input to an bit
decoder. This circuit is equivalent to a

A. -bit binary up counter. B. -bit binary down counter.

C. --bit ring counter. D. -bit Johnson counter.
gatecse-2014-set2 digital-logic normal digital-counter

Answer key☟

6.11.9 Digital Counter: GATE CSE 2015 Set 1 | Question: 20

Consider a -bit Johnson counter with an initial value of The counting sequence of this counter is

A. B.
C. D.
gatecse-2015-set1 digital-logic digital-counter easy

Answer key☟

6.11.10 Digital Counter: GATE CSE 2015 Set 2 | Question: 7

The minimum number of flip-flops required to construct a synchronous counter with the count sequence
 is _______.

gatecse-2015-set2 digital-logic digital-counter normal numerical-answers

Answer key☟

6.11.11 Digital Counter: GATE CSE 2016 Set 1 | Question: 8

We want to design a synchronous counter that counts the sequence and then
repeats. The minimum number of flip-flops required to implement this counter is _____________.

gatecse-2016-set1 digital-logic digital-counter flip-flop normal numerical-answers

Answer key☟

6.11.12 Digital Counter: GATE CSE 2017 Set 2 | Question: 42

The next state table of a bit saturating up-counter is given below.

The counter is built as a synchronous sequential circuit using flip-flops. The expressions for and are

A.
B.
C.
D.

gatecse-2017-set2 digital-logic digital-counter

Answer key☟

6.11.13 Digital Counter: GATE CSE 2021 Set 1 | Question: 28

Consider a -bit counter, designed using flip-flops, as shown below:

Assuming the initial state of the counter given by as , what are the next three states?

A. B. C. D.
gatecse-2021-set1 digital-logic sequential-circuit digital-counter 2-marks

Answer key☟

6.11.14 Digital Counter: GATE CSE 2023 | Question: 33

Consider a sequential digital circuit consisting of flip-flops and flip-flops as shown in the figure.
is the clock input to the circuit. At the beginning, and have values and respectively.
 Which one of the given values of can be obtained with this digital circuit?

A. B. C. D.
gatecse-2023 digital-logic flip-flop 2-marks digital-counter

Answer key☟

6.11.15 Digital Counter: GATE IT 2005 | Question: 11

How many pulses are needed to change the contents of a -bit up counter from to
(rightmost bit is the LSB)?

A. B. C. D.
gateit-2005 digital-logic digital-counter normal

Answer key☟

6.11.16 Digital Counter: GATE IT 2008 | Question: 37

Consider the following state diagram and its realization by a JK flip flop

The combinational circuit generates J and K in terms of x, y and Q.

The Boolean expressions for J and K are :

A. and B. and
C. and D. and
gateit-2008 digital-logic boolean-algebra normal digital-counter

Answer key☟

6.11.17 Digital Counter: GATE1992-04-c

Design a -bit counter using D-flip flops such that not more than one flip-flop changes state between any two
consecutive states.

gate1992 digital-logic sequential-circuit flip-flop digital-counter normal descriptive

Answer key☟

6.12 Finite State Machines (4)

6.12.1 Finite State Machines: GATE CSE 1994 | Question: 3.3

State True or False with one line explanation

A FSM (Finite State Machine) can be designed to add two integers of any arbitrary length (arbitrary number of
digits).

gate1994 digital-logic normal true-false finite-state-machines

Answer key☟
6.12.2 Finite State Machines: GATE CSE 1995 | Question: 2.23

A finite state machine with the following state table has a single input and a single out .

If the initial state is unknown, then the shortest input sequence to reach the final state is:

A. B. C. D.
gate1995 digital-logic normal finite-state-machines

Answer key☟

6.12.3 Finite State Machines: GATE CSE 1996 | Question: 2.23

Consider the following state table for a sequential machine. The number of states in the minimized machine
will be

A. B. C. D.
gate1996 normal digital-logic finite-state-machines

Answer key☟

6.12.4 Finite State Machines: GATE CSE 2009 | Question: 27

Given the following state table of an FSM with two states and ,one input and one output.

If the initial state is what is the minimum length of an input string which will take the machine to the
state with .

A. B. C. D.
gatecse-2009 digital-logic normal finite-state-machines
 Answer key☟

6.13 Fixed Point Representation (2)

6.13.1 Fixed Point Representation: GATE CSE 2017 Set 1 | Question: 7

The n-bit fixed-point representation of an unsigned real number uses bits for the fraction part. Let
. The range of decimal values for in this representation is

A. to B. to
C. 0 to D. 0 to
gatecse-2017-set1 digital-logic number-representation fixed-point-representation

Answer key☟

6.13.2 Fixed Point Representation: GATE CSE 2018 | Question: 33

Consider the unsigned 8-bit fixed point binary number representation, below,

where the position of the primary point is between and . Assume is the most significant bit. Some of the
decimal numbers listed below cannot be represented exactly in the above representation:

i.
ii.
iii.
iv.

Which one of the following statements is true?

A. None of can be exactly represented

B. Only cannot be exactly represented
C. Only and cannot be exactly represented
D. Only and cannot be exactly represented

gatecse-2018 digital-logic number-representation fixed-point-representation normal 2-marks

Answer key☟

6.14 Flip Flop (6)

6.14.1 Flip Flop: GATE CSE 2001 | Question: 11

A sequential circuit takes an input stream of and and produces an output stream of and
Initially it replicates the input on its output until two consecutive are encountered on the input. From then
onward, it produces an output stream, which is the bit-wise complement of input stream until it encounters two
consecutive 1's, whereupon the process repeats. An example input and output stream is shown below.

master-slave flip-flops are to be used to design the circuit.

a. Give the state transition diagram

b. Give the minimized sum-of-product expression for and inputs of one of its state flip-flops

gatecse-2001 digital-logic normal descriptive flip-flop

Answer key☟

6.14.2 Flip Flop: GATE CSE 2004 | Question: 18, ISRO2007-31

In an latch made by cross-coupling two NAND gates, if both and inputs are set to , then it will
result in

A. B.
C. D. Indeterminate states
gatecse-2004 digital-logic easy isro2007 flip-flop

Answer key☟

6.14.3 Flip Flop: GATE CSE 2015 Set 1 | Question: 37

A positive edge-triggered flip-flop is connected to a positive edge-triggered flip-flop as follows. The

output of the flip-flop is connected to both the and inputs of the flip-flop, while the output of
the flip-flop is connected to the input of the flip-flop. Initially, the output of the flip-flop is set to logic one
and the output of the flip-flop is cleared. Which one of the following is the bit sequence (including the initial
state) generated at the output of the flip-flop when the flip-flops are connected to a free-running common
clock? Assume that is the toggle mode and is the state holding mode of the flip-
flops. Both the flip-flops have non-zero propagation delays.

A. B.
C. D.
gatecse-2015-set1 digital-logic flip-flop normal

Answer key☟

6.14.4 Flip Flop: GATE CSE 2017 Set 1 | Question: 33

Consider a combination of and flip-flops connected as shown below. The output of the flip-flop is
connected to the input of the flip-flop and the output of the flip-flop is connected to the input of the
flip-flop.

Initially, both and are set to (before the clock cycle). The outputs

A. after the cycle are and after the cycle are respectively.
B. after the cycle are and after the cycle are respectively.
C. after the cycle are and after the cycle are respectively.
D. after the cycle are and after the cycle are respectively.

gatecse-2017-set1 digital-logic flip-flop normal

Answer key☟

6.14.5 Flip Flop: GATE CSE 2018 | Question: 22

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered
flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on
some value of "in" is ____

gatecse-2018 digital-logic flip-flop numerical-answers normal 1-mark

Answer key☟
 6.14.6 Flip Flop: GATE IT 2007 | Question: 7

Which of the following input sequences for a cross-coupled flip-flop realized with two gates
may lead to an oscillation?

A. B. C. D.
gateit-2007 digital-logic normal flip-flop

Answer key☟

6.15 Floating Point Representation (8)

6.15.1 Floating Point Representation: GATE CSE 1987 | Question: 1-vii

The exponent of a floating-point number is represented in excess- code so that:

A. The dynamic range is large. B. The precision is high.

C. The smallest number is D. Overflow is avoided.
represented by all zeros.
gate1987 digital-logic number-representation floating-point-representation

Answer key☟

6.15.2 Floating Point Representation: GATE CSE 1989 | Question: 1-vi

Consider an excess - representation for floating point numbers with BCD digit mantissa and BCD digit
exponent in normalised form. The minimum and maximum positive numbers that can be represented are
__________ and _____________ respectively.

descriptive gate1989 digital-logic number-representation floating-point-representation

Answer key☟

6.15.3 Floating Point Representation: GATE CSE 1990 | Question: 1-iv-a

A -bit floating-point number is represented by a -bit signed exponent, and a -bit fractional mantissa.
The base of the scale factor is
The range of the exponent is ___________

gate1990 digital-logic number-representation floating-point-representation fill-in-the-blanks

Answer key☟

6.15.4 Floating Point Representation: GATE CSE 1990 | Question: 1-iv-b

A -bit floating-point number is represented by a -bit signed exponent, and a -bit fractional mantissa.
The base of the scale factor is
The range of the exponent is ___________, if the scale factor is represented in excess- format.

gate1990 digital-logic number-representation floating-point-representation fill-in-the-blanks

Answer key☟

6.15.5 Floating Point Representation: GATE CSE 1997 | Question: 72

Following floating point number format is given

is a fraction represented by a mantissa (includes sign bit) in sign magnitude form, is a
exponent (includes sign hit) in sign magnitude form and is a floating point number. Let
in decimal and in decimal

a. Represent and as floating point numbers in the above format.

b. Show the steps involved in floating point addition of and
c. What is the percentage error (up to one position beyond decimal point) in the addition operation in (b)?

gate1997 digital-logic floating-point-representation normal descriptive

Answer key☟
 6.15.6 Floating Point Representation: GATE CSE 2003 | Question: 43

The following is a scheme for floating point number representation using bits.

Let and be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then
the floating point number represented is:

What is the maximum difference between two successive real numbers representable in this system?

A. B. C. D.
gatecse-2003 digital-logic number-representation floating-point-representation normal

Answer key☟

6.15.7 Floating Point Representation: GATE CSE 2005 | Question: 85-a

Consider the following floating-point format.

Mantissa is a pure fraction in sign-magnitude form.

The decimal number has the following hexadecimal representation (without normalization and
rounding off):

A. B. C. D.
gatecse-2005 digital-logic number-representation floating-point-representation normal

Answer key☟

6.15.8 Floating Point Representation: GATE CSE 2005 | Question: 85-b

Consider the following floating-point format.

Mantissa is a pure fraction in sign-magnitude form.

The normalized representation for the above format is specified as follows. The mantissa has an implicit
preceding the binary (radix) point. Assume that only are padded in while shifting a field.
The normalized representation of the above number is:

A. B. C. D.
gatecse-2005 digital-logic number-representation floating-point-representation normal

Answer key☟

6.16 Functional Completeness (7)

6.16.1 Functional Completeness: GATE CSE 1989 | Question: 4-iii

Show that {NOR} is a functionally complete set of Boolean operations.

gate1989 descriptive digital-logic functional-completeness

Answer key☟

6.16.2 Functional Completeness: GATE CSE 1992 | Question: 02-ii

All digital circuits can be realized using only

A. Ex-OR gates B. Multiplexers C. Half adders D. OR gates

gate1992 normal digital-logic digital-circuits multiple-selects functional-completeness combinational-circuit

Answer key☟

6.16.3 Functional Completeness: GATE CSE 1993 | Question: 9

Assume that only half adders are available in your laboratory. Show that any binary function can be
implemented using half adders only.

gate1993 digital-logic combinational-circuit adder descriptive functional-completeness

Answer key☟

6.16.4 Functional Completeness: GATE CSE 1998 | Question: 5

The implication gate, shown below has two inputs ( ; the output is 1 except when
using only four implication gates.

Show that the implication gate is functionally complete.

gate1998 digital-logic functional-completeness descriptive

Answer key☟

6.16.5 Functional Completeness: GATE CSE 1999 | Question: 2.9

Which of the following sets of component(s) is/are sufficient to implement any arbitrary Boolean function?

A. XOR gates, NOT gates

B. to multiplexers
C. AND gates, XOR gates
D. Three-input gates that output for the inputs and .

gate1999 digital-logic normal functional-completeness multiple-selects

Answer key☟

6.16.6 Functional Completeness: GATE CSE 2015 Set 1 | Question: 39

Consider the operations

and
Which one of the following is correct?

A. Both and are functionally complete

B. Only is functionally complete
C. Only is functionally complete
D. Neither nor is functionally complete
 gatecse-2015-set1 boolean-algebra difficult functional-completeness

Answer key☟

6.16.7 Functional Completeness: GATE IT 2008 | Question: 1

A set of Boolean connectives is functionally complete if all Boolean functions can be synthesized using
those. Which of the following sets of connectives is NOT functionally complete?

A. EX-NOR B. implication, negation

C. OR, negation D. NAND
gateit-2008 digital-logic easy functional-completeness

Answer key☟

6.17 IEEE Representation (11)

6.17.1 IEEE Representation: GATE CSE 2008 | Question: 4

In the IEEE floating point representation the hexadecimal value corresponds to

A. The normalized value B. The normalized value

C. The normalized value D. The special value
gatecse-2008 digital-logic floating-point-representation ieee-representation easy

Answer key☟

6.17.2 IEEE Representation: GATE CSE 2012 | Question: 7

The decimal value in IEEE single precision floating point representation has

A. fraction bits of and exponent value of

B. fraction bits of and exponent value of
C. fraction bits of and exponent value of
D. no exact representation

gatecse-2012 digital-logic normal number-representation ieee-representation

Answer key☟

6.17.3 IEEE Representation: GATE CSE 2014 Set 2 | Question: 45

The value of a type variable is represented using the single-precision floating point format of
standard that uses for sign, for biased exponent and for the mantissa. A
type variable is assigned the decimal value of . The representation of in hexadecimal notation is

A. B. C. D.
gatecse-2014-set2 digital-logic number-representation normal ieee-representation

Answer key☟

6.17.4 IEEE Representation: GATE CSE 2017 Set 2 | Question: 12

Given the following binary number in -bit (single precision) format :

The decimal value closest to this floating-point number is :

A. B. C. D.
gatecse-2017-set2 digital-logic number-representation floating-point-representation ieee-representation

Answer key☟
6.17.5 IEEE Representation: GATE CSE 2020 | Question: 29

Consider three registers , , and that store numbers in single precision floating point
format. Assume that and contain the values (in hexadecimal notation) and
respectively.
If , what is the value stored in ?

A. B. C. D.
gatecse-2020 floating-point-representation digital-logic 2-marks ieee-representation

Answer key☟

6.17.6 IEEE Representation: GATE CSE 2021 Set 1 | Question: 24

Consider the following representation of a number in single-precision floating point format with a
bias of .

Here and denote the sign, exponent, and fraction components of the floating point representation.

The decimal value corresponding to the above representation (rounded to decimal places) is ____________.

gatecse-2021-set1 digital-logic number-representation ieee-representation numerical-answers 1-mark floating-point-representation

Answer key☟

6.17.7 IEEE Representation: GATE CSE 2021 Set 2 | Question: 4

The format of the single-precision floating point representation of a real number as per the
standard is as follows:

Which one of the following choices is correct with respect to the smallest normalized positive number represented
using the standard?

A. exponent and mantissa

B. exponent and mantissa
C. exponent and mantissa
D. exponent and mantissa

gatecse-2021-set2 digital-logic number-representation ieee-representation 1-mark floating-point-representation

Answer key☟

6.17.8 IEEE Representation: GATE CSE 2022 | Question: 31

Consider three floating point numbers and stored in registers and respectively as per
single precision floating point format. The content stored in these registers
are as follows.

Which one of the following is

A. B. C. D.
gatecse-2022 digital-logic ieee-representation number-representation 2-marks floating-point-representation

Answer key☟

6.17.9 IEEE Representation: GATE CSE 2023 | Question: 35

Consider the single precision floating point numbers and

Which one of the following corresponds to the product of these numbers represented in the
 single precision format?

A. B. C. D.
gatecse-2023 digital-logic number-representation ieee-representation 2-marks floating-point-representation

Answer key☟

6.17.10 IEEE Representation: GATE CSE 2024 | Set 2 | Question: 4

​The format of a single-precision floating-point number as per the standard is:

Sign Exponent Mantissa

Choose the largest floating-point number among the following options.

A.
Sign Exponent Mantissa

B.
Sign Exponent Mantissa

C.
Sign Exponent Mantissa

D.
Sign Exponent Mantissa

gatecse2024-set2 digital-logic number-representation ieee-representation floating-point-representation

Answer key☟

6.17.11 IEEE Representation: GATE IT 2008 | Question: 7

The following bit pattern represents a floating point number in IEEE single precision format

The value of the number in decimal form is

A. B. C. D. None of the above

gateit-2008 digital-logic number-representation floating-point-representation ieee-representation normal

Answer key☟

6.18 K Map (19)

6.18.1 K Map: GATE CSE 1987 | Question: 16-a

A Boolean function is to be realized only by gates. Its -map is given below:

The realization is

A. B.
 C. D.

gate1987 digital-logic k-map

Answer key☟

6.18.2 K Map: GATE CSE 1988 | Question: 3a-b

The Karnaugh map of a function of is shown on the left hand side of the above figure.
The reduced form of the same map is shown on the right hand side, in which the variable is entered in the map
itself. Discuss,

a. The methodology by which the reduced map has been derived and
b. the rules (or steps) by which the boolean function can be derived from the entries in the reduced map.

gate1988 descriptive digital-logic k-map

Answer key☟

6.18.3 K Map: GATE CSE 1992 | Question: 01-i

The Boolean function in sum of products form where K-map is given below (figure) is _______

gate1992 digital-logic k-map normal fill-in-the-blanks

Answer key☟

6.18.4 K Map: GATE CSE 1995 | Question: 15-a

Implement a circuit having the following output expression using an inverter and a nand gate

gate1995 digital-logic k-map normal descriptive

Answer key☟

6.18.5 K Map: GATE CSE 1995 | Question: 15-b

What is the equivalent minimal Boolean expression (in sum of products form) for the Karnaugh map given
below?
 gate1995 digital-logic boolean-algebra k-map normal descriptive

Answer key☟

6.18.6 K Map: GATE CSE 1996 | Question: 2.24

What is the equivalent Boolean expression in product-of-sums form for the Karnaugh map given in Fig

A. B.

C. D.
gate1996 digital-logic k-map easy

Answer key☟

6.18.7 K Map: GATE CSE 1998 | Question: 2.7

The function represented by the Karnaugh map given below is

A. B. C. D.
gate1998 digital-logic k-map normal

Answer key☟

6.18.8 K Map: GATE CSE 1999 | Question: 1.8

Which of the following functions implements the Karnaugh map shown below?

A. B.
C. D.
gate1999 digital-logic k-map easy

Answer key☟
6.18.9 K Map: GATE CSE 2000 | Question: 2.11

Which functions does NOT implement the Karnaugh map given below?

A. B.
C. D. None of the above
gatecse-2000 digital-logic k-map normal

Answer key☟

6.18.10 K Map: GATE CSE 2001 | Question: 1.11

Given the following karnaugh map, which one of the following represents the minimal Sum-Of-Products of
the map?

A. B. C. D.
gatecse-2001 k-map digital-logic normal

Answer key☟

6.18.11 K Map: GATE CSE 2002 | Question: 1.12

Minimum sum of product expression for shown in Karnaugh-map below

A. B. C. D. None of the above

gatecse-2002 digital-logic k-map normal

Answer key☟

6.18.12 K Map: GATE CSE 2003 | Question: 45

The literal count of a Boolean expression is the sum of the number of times each literal appears in the
expression. For example, the literal count of is What are the minimum possible literal counts
of the product-of-sum and sum-of-product representations respectively of the function given by the following
Karnaugh map? Here, denotes "don't care"
 A. B. C. D.
gatecse-2003 digital-logic k-map normal

Answer key☟

6.18.13 K Map: GATE CSE 2008 | Question: 5

In the Karnaugh map shown below, denotes a don’t care term. What is the minimal form of the function
represented by the Karnaugh map?

A. B.
C. D.
gatecse-2008 digital-logic k-map easy

Answer key☟

6.18.14 K Map: GATE CSE 2012 | Question: 30

What is the minimal form of the Karnaugh map shown below? Assume that denotes a don’t care term

A. B.
C. D.
gatecse-2012 digital-logic k-map easy

Answer key☟

6.18.15 K Map: GATE CSE 2017 Set 1 | Question: 21

Consider the Karnaugh map given below, where represents "don't care" and blank represents .
Assume for all inputs , the respective complements are also available. The above logic is
implemented using -input gates only. The minimum number of gates required is ____________ .

gatecse-2017-set1 digital-logic k-map numerical-answers normal

Answer key☟

6.18.16 K Map: GATE CSE 2019 | Question: 30

Consider three -variable functions , and , which are expressed in sum-of-minterms as

For the following circuit with one AND gate and one XOR gate the output function can be expressed as:

A. B.
C. D.
gatecse-2019 digital-logic k-map digital-circuits 2-marks

Answer key☟

6.18.17 K Map: GATE IT 2006 | Question: 35

The boolean function for a combinational circuit with four inputs is represented by the following Karnaugh
map.

Which of the product terms given below is an essential prime implicant of the function?

A. B. C. D.
gateit-2006 digital-logic k-map normal

Answer key☟

6.18.18 K Map: GATE IT 2007 | Question: 78

Consider the following expression

Which of the following Karnaugh Maps correctly represents the expression?

A. B. C. D.
 gateit-2007 digital-logic k-map normal

Answer key☟

6.18.19 K Map: GATE IT 2007 | Question: 79

Consider the following expression

Which of the following expressions does not correspond to the Karnaugh Map obtained for the given expression?

A.
B.
C.
D.

gateit-2007 digital-logic k-map normal

Answer key☟

6.19 Memory Interfacing (4)

6.19.1 Memory Interfacing: GATE CSE 1995 | Question: 2.2

The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How
many separate address and data lines are needed for a memory of ?

A. address, data lines B. address, data lines

C. address, data lines D. address, data lines
gate1995 digital-logic memory-interfacing normal

Answer key☟

6.19.2 Memory Interfacing: GATE CSE 2009 | Question: 7, ISRO2015-3

How many RAM chips are needed to provide a memory capacity of bytes?

A. B. C. D.
gatecse-2009 digital-logic memory-interfacing easy isro2015

Answer key☟

6.19.3 Memory Interfacing: GATE CSE 2010 | Question: 7

The main memory unit with a capacity of is built using DRAM chips. Each DRAM
chip has rows of cells with cells in each row. The time taken for a single refresh operation is
. The time required to perform one refresh operation on all the cells in the memory unit is

A. nanoseconds B. nanoseconds
C. nanoseconds D. nanoseconds
gatecse-2010 digital-logic memory-interfacing normal

Answer key☟

6.19.4 Memory Interfacing: GATE IT 2005 | Question: 9

A dynamic RAM has a memory cycle time of . It has to be refreshed times per msec and each
refresh takes . What percentage of the memory cycle time is used for refreshing?

A. B. C. D.
 gateit-2005 digital-logic memory-interfacing normal

Answer key☟

6.20 Min No Gates (4)

6.20.1 Min No Gates: GATE CSE 2000 | Question: 9

Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not
detect illegal input):

A. Write the truth table for all bits. Label the input bits with as the least significant bit. Label the output
bits with as the least significant bit. Use to signify truth.
B. Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input OR gate and
two NOT gates.

gatecse-2000 digital-logic min-no-gates descriptive

Answer key☟

6.20.2 Min No Gates: GATE CSE 2004 | Question: 58

A circuit outputs a digit in the form of bits. is represented by by by . A

combinational circuit is to be designed which takes these bits as input and outputs if the digit , and
otherwise. If only and gates may be used, what is the minimum number of gates required?

A. B. C. D.
gatecse-2004 digital-logic normal min-no-gates

Answer key☟

6.20.3 Min No Gates: GATE CSE 2009 | Question: 6

What is the minimum number of gates required to implement the Boolean function if we have to
use only gates?

A. B. C. D.
gatecse-2009 digital-logic min-no-gates normal

Answer key☟

6.20.4 Min No Gates: GATE IT 2004 | Question: 8

What is the minimum number of gates required to implement a

function without using any other logic gate?

A. B. C. D.
gateit-2004 digital-logic min-no-gates normal

Answer key☟

6.21 Min Product of Sums (2)

6.21.1 Min Product of Sums: GATE CSE 1990 | Question: 5-a

Find the minimum product of sums of the following expression

gate1990 digital-logic boolean-algebra min-product-of-sums canonical-normal-form descriptive

Answer key☟
 6.21.2 Min Product of Sums: GATE CSE 2017 Set 2 | Question: 28

G i ve n ; where represents the 'don't-care'

condition in Karnaugh maps. Which of the following is a minimum product-of-sums (POS) form of
?

A. B.
C. D.
gatecse-2017-set2 digital-logic min-product-of-sums

Answer key☟

6.22 Min Sum of Products Form (14)

6.22.1 Min Sum of Products Form: GATE CSE 1988 | Question: 2-v

Three switching functions and are expressed below as sum of minterms.

Express the function realised by the circuit shown in the below figure as the sum of minterms (in decimal
notation).

gate1988 descriptive digital-logic easy circuit-output min-sum-of-products-form

Answer key☟

6.22.2 Min Sum of Products Form: GATE CSE 1991 | Question: 5-b

Find the minimum sum of products form of the logic function

where and represent minterm and don't
care term respectively.

gate1991 digital-logic boolean-algebra min-sum-of-products-form descriptive

Answer key☟

6.22.3 Min Sum of Products Form: GATE CSE 1997 | Question: 71

Let

A. Express as the minimal sum of products. Write only the answer.

B. If the output line is stuck at , for how many input combinations will the value of be correct?

gate1997 digital-logic min-sum-of-products-form numerical-answers

Answer key☟

6.22.4 Min Sum of Products Form: GATE CSE 2001 | Question: 10

a. Is the function its self-dual? Justify your answer.

b. Give a minimal product-of-sum form of the output of the following to converter.
 gatecse-2001 digital-logic normal descriptive min-sum-of-products-form

Answer key☟

6.22.5 Min Sum of Products Form: GATE CSE 2005 | Question: 18

The switching expression corresponding to is:

A. B.
C. D.
gatecse-2005 digital-logic normal min-sum-of-products-form

Answer key☟

6.22.6 Min Sum of Products Form: GATE CSE 2007 | Question: 9

Consider the following Boolean function of four variables:

The function is

A. independent of one variables. B. independent of two variables.

C. independent of three variables. D. dependent on all variables
gatecse-2007 digital-logic normal min-sum-of-products-form k-map

Answer key☟

6.22.7 Min Sum of Products Form: GATE CSE 2011 | Question: 14

The simplified SOP (Sum of Product) from the Boolean expression

is

A. B. C. D.
gatecse-2011 digital-logic normal min-sum-of-products-form

Answer key☟

6.22.8 Min Sum of Products Form: GATE CSE 2014 Set 1 | Question: 45

Consider the multiplexer with two select lines and given below

The minimal sum-of-products form of the Boolean expression for the output of the multiplexer is

A. B.
C. D.
 gatecse-2014-set1 digital-logic normal multiplexer min-sum-of-products-form

Answer key☟

6.22.9 Min Sum of Products Form: GATE CSE 2014 Set 1 | Question: 7

Consider the following Boolean expression for F:

The minimal sum of products form of is

A. B.
C. D.
gatecse-2014-set1 digital-logic normal min-sum-of-products-form

Answer key☟

6.22.10 Min Sum of Products Form: GATE CSE 2014 Set 3 | Question: 7

Consider the following minterm expression for :

The minterms , , and are 'do not care' terms. The minimal sum-of-products form for is

A. B.
C. D.
gatecse-2014-set3 digital-logic min-sum-of-products-form normal

Answer key☟

6.22.11 Min Sum of Products Form: GATE CSE 2018 | Question: 49

Consider the minterm list form of a Boolean function given below.

Here, denotes a minterm and denotes a don't care term. The number of essential prime implicants of the
function is ___

gatecse-2018 digital-logic min-sum-of-products-form numerical-answers 2-marks

Answer key☟

6.22.12 Min Sum of Products Form: GATE CSE 2021 Set 2 | Question: 52

Consider a Boolean function such that

The number of literals in the minimal sum-of-products expression of is _________

gatecse-2021-set2 digital-logic boolean-algebra min-sum-of-products-form numerical-answers 2-marks

Answer key☟

6.22.13 Min Sum of Products Form: GATE CSE 2024 | Set 1 | Question: 37

Consider a Boolean expression given by .

Which of the following statements is/are CORRECT?

A. B.
 C. is independent of input D. is independent of input

gatecse2024-set1 multiple-selects digital-logic min-sum-of-products-form

Answer key☟

6.22.14 Min Sum of Products Form: GATE IT 2008 | Question: 8

Consider the following Boolean function of four variables

The function is

A. independent of one variable B. independent of two variables

C. independent of three variable D. dependent on all the variables
gateit-2008 digital-logic normal min-sum-of-products-form

Answer key☟

6.23 Multiplexer (14)

6.23.1 Multiplexer: GATE CSE 1990 | Question: 5-b

Show with the help of a block diagram how the Boolean function :

can be realised using only a multiplexer.

gate1990 descriptive digital-logic combinational-circuit multiplexer

Answer key☟

6.23.2 Multiplexer: GATE CSE 1998 | Question: 1.14

A multiplexer with a data select input is a

A. multiplexer B. multiplexer
C. multiplexer D. multiplexer
gate1998 digital-logic multiplexer easy

Answer key☟

6.23.3 Multiplexer: GATE CSE 2001 | Question: 2.11

Consider the circuit shown below. The output of a MUX is given by the function .

Which of the following is true?

A. B.
C. D.
gatecse-2001 digital-logic normal multiplexer

Answer key☟

6.23.4 Multiplexer: GATE CSE 2004 | Question: 60

Consider a multiplexer with and as data inputs and the as the control input. selects input ,
and selects input . What are the connections required to realize the 2-variable Boolean function
, without using any additional hardware?
 A. B.
C. D.
gatecse-2004 digital-logic normal multiplexer

Answer key☟

6.23.5 Multiplexer: GATE CSE 2007 | Question: 34

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of
variables. What is the minimum size of the multiplexer needed?

A. line to line B. line to line

C. line to line D. line to line
gatecse-2007 digital-logic normal multiplexer

Answer key☟

6.23.6 Multiplexer: GATE CSE 2016 Set 1 | Question: 30

Consider the two cascade to multiplexers as shown in the figure .

The minimal sum of products form of the output is

A. B.
C. D.
gatecse-2016-set1 digital-logic multiplexer normal

Answer key☟

6.23.7 Multiplexer: GATE CSE 2020 | Question: 19

A multiplexer is placed between a group of registers and an accumulator to regulate data movement
such that at any given point in time the content of only one register will move to the accumulator. The
number of select lines needed for the multiplexer is ______.

gatecse-2020 numerical-answers digital-logic multiplexer 1-mark

Answer key☟

6.23.8 Multiplexer: GATE CSE 2021 Set 2 | Question: 5

Which one of the following circuits implements the Boolean function given below?
, where is the minterm.

A. B.

C. D.
gatecse-2021-set2 digital-logic combinational-circuit multiplexer 1-mark

Answer key☟
6.23.9 Multiplexer: GATE CSE 2023 | Question: 11

The output of a -input multiplexer is connected back to one of its inputs as shown in the figure.

Match the functional equivalence of this circuit to one of the following options.

A. Flip-flop B. Latch C. Half-adder D. Demultiplexer

gatecse-2023 digital-logic combinational-circuit multiplexer 1-mark

Answer key☟

6.23.10 Multiplexer: GATE CSE 2023 | Question: 34

A Boolean digital circuit is composed using two -input multiplexers and one -input
multiplexer as shown in the figure. are the inputs of the multiplexers and could
be connected to either or The select lines of the multiplexers are connected to Boolean variables
as shown.

Which one of the following set of values of will realise the Boolean function

A. B.
C. D.
gatecse-2023 digital-logic combinational-circuit multiplexer 2-marks

Answer key☟

6.23.11 Multiplexer: GATE CSE 2024 | Set 1 | Question: 54

Consider a digital logic circuit consisting of three -to- multiplexers , and as shown below.
and are inputs of . and are inputs of . , and are select lines of , and ,
respectively.
For an instance of inputs , and , the number of combinations of that
give the output is ____________.

gatecse2024-set1 numerical-answers digital-logic multiplexer

Answer key☟

6.23.12 Multiplexer: GATE IT 2005 | Question: 48

The circuit shown below implements a NOR gate using two MUX (control signal selects the
upper input). What are the values of signals and ?

A. B. C. D.
gateit-2005 digital-logic normal multiplexer

Answer key☟

6.23.13 Multiplexer: GATE IT 2007 | Question: 8

The following circuit implements a two-input AND gate using two multiplexers.

What are the values of ?

A. B.
C. D.
gateit-2007 digital-logic normal multiplexer

Answer key☟
 6.23.14 Multiplexer: GATE1992-04-b

A priority encoder accepts three input signals and produces a two-bit output
corresponding to the highest priority active input signal. Assume has the highest priority followed by
and has the lowest priority. If none of the inputs are active the output should be , design the priority encoder
using multiplexers as the main components.

gate1992 digital-logic combinational-circuit multiplexer descriptive

Answer key☟

6.24 Number Representation (57)

6.24.1 Number Representation: GATE CSE 1988 | Question: 2-vi

Define the value of in the following:

gate1988 digital-logic normal number-representation descriptive

Answer key☟

6.24.2 Number Representation: GATE CSE 1990 | Question: 1-viii

The condition for overflow in the addition of two complement numbers in terms of the carry generated by
the two most significant bits is ___________.

gate1990 digital-logic number-representation fill-in-the-blanks

Answer key☟

6.24.3 Number Representation: GATE CSE 1991 | Question: 01-iii

Consider the number given by the decimal expression:

The number of in the unsigned binary representation of the number is ______

gate1991 digital-logic number-representation normal numerical-answers

Answer key☟

6.24.4 Number Representation: GATE CSE 1991 | Question: 01-v

When two -bit numbers and are multiplied, the bit of the product is
given by ________

gate1991 digital-logic normal number-representation fill-in-the-blanks

Answer key☟

6.24.5 Number Representation: GATE CSE 1992 | Question: 4-a

Consider addition in two's complement arithmetic. A carry from the most significant bit does not always
correspond to an overflow. Explain what is the condition for overflow in two's complement arithmetic.

gate1992 digital-logic normal number-representation descriptive

Answer key☟

6.24.6 Number Representation: GATE CSE 1993 | Question: 6.5

Convert the following numbers in the given bases into their equivalents in the desired bases:

A.
B.

gate1993 digital-logic number-representation normal descriptive

 Answer key☟

6.24.7 Number Representation: GATE CSE 1994 | Question: 2.7

Consider -bit (including sign bit) complement representation of integer numbers. The range of integer
values, , that can be represented is ______ ______ .

gate1994 digital-logic number-representation easy fill-in-the-blanks

Answer key☟

6.24.8 Number Representation: GATE CSE 1995 | Question: 18

The following is an incomplete Pascal function to convert a given decimal integer (in the range to )
into a binary integer in ’s complement representation. Determine the expressions that complete
program.
function TWOSCOMP (N:integer):integer;
var
REM, EXPONENT:integer;
BINARY :integer;
begin
if(N>=-8) and (N<=+7) then
begin
if N<0 then
N:=A;
BINARY:=0;
EXPONENT:=1;
while N<>0 do
begin
REM:=N mod 2;
BINARY:=BINARY + B*EXPONENT;
EXPONENT:=EXPONENT*10;
N:=C
end
TWOSCOMP:=BINARY
end
end;

gate1995 digital-logic number-representation normal descriptive

Answer key☟

6.24.9 Number Representation: GATE CSE 1995 | Question: 2.12, ISRO2015-9

The number of 's in the binary representation of are:

A. B. C. D.
gate1995 digital-logic number-representation normal isro2015

Answer key☟

6.24.10 Number Representation: GATE CSE 1996 | Question: 1.25

Consider the following floating-point number representation.

The exponent is in complement representation and the mantissa is in the sign-magnitude representation. The
range of the magnitude of the normalized numbers in this representation is

A. to B. to C. to D. to
gate1996 digital-logic number-representation normal

Answer key☟
6.24.11 Number Representation: GATE CSE 1997 | Question: 5.4

Given .
The value of the radix is:

A. B. C. D.
gate1997 digital-logic number-representation normal

Answer key☟

6.24.12 Number Representation: GATE CSE 1998 | Question: 1.17

The octal representation of an integer is . If this were to be treated as an eight-bit integer in an

based computer, its decimal equivalent is

A. B. C. D.
gate1998 digital-logic number-representation normal

Answer key☟

6.24.13 Number Representation: GATE CSE 1998 | Question: 2.20

Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of
reduction in storage space of this attribute if it is stored as an integer rather than in character form?

A. B. C. D.
gate1998 digital-logic number-representation normal

Answer key☟

6.24.14 Number Representation: GATE CSE 1999 | Question: 2.17

Zero has two representations in

A. Sign-magnitude B. complement
C. complement D. None of the above
gate1999 digital-logic number-representation easy multiple-selects

Answer key☟

6.24.15 Number Representation: GATE CSE 2000 | Question: 1.6

The number in complement representation is

A. B. C. D.
gatecse-2000 digital-logic number-representation easy

Answer key☟

6.24.16 Number Representation: GATE CSE 2000 | Question: 2.14

Consider the values of and the sequence

X:= A + B Y:= A + C
X:= X + C Y:= Y + B

executed on a computer where floating point numbers are represented with bits. The values for and will be

A. B.
C. D.
gatecse-2000 digital-logic number-representation normal

Answer key☟

6.24.17 Number Representation: GATE CSE 2001 | Question: 2.10

The complement representation of (-539)10 in hexadecimal is

 A. B. C. D.
gatecse-2001 digital-logic number-representation easy

Answer key☟

6.24.18 Number Representation: GATE CSE 2002 | Question: 1.14

The decimal value

A. is equivalent to the binary value

B. is equivalent to the binary value
C. is equivalent to the binary value
D. cannot be represented precisely in binary

gatecse-2002 digital-logic number-representation easy

Answer key☟

6.24.19 Number Representation: GATE CSE 2002 | Question: 1.15

The complement representation of the decimal value is

A. B. C. D.
gatecse-2002 digital-logic number-representation easy

Answer key☟

6.24.20 Number Representation: GATE CSE 2002 | Question: 1.16

Sign extension is a step in

A. floating point multiplication B. signed bit integer addition

C. arithmetic left shift D. converting a signed integer from
one size to another
gatecse-2002 digital-logic easy number-representation

Answer key☟

6.24.21 Number Representation: GATE CSE 2002 | Question: 1.21

In complement addition, overflow

A. is flagged whenever there is carry from sign bit addition

B. cannot occur when a positive value is added to a negative value
C. is flagged when the carries from sign bit and previous bit match
D. None of the above

gatecse-2002 digital-logic number-representation normal

Answer key☟

6.24.22 Number Representation: GATE CSE 2002 | Question: 9

Consider the following floating-point representation scheme as shown in the format below. A value is
specified by fields, a one bit sign field (with for positive and for negative values), a fraction field
(with the binary point is at the left end of the fraction bits), and a exponent field (in signed integer
representation, with is the base of exponentiation). The sign bit is the most significant bit.

A. It is required to represent the decimal value as a normalized floating point number in the given format.
Derive the values of the various fields. Express your final answer in the hexadecimal.
B. What is the largest value that can be represented using this format? Express your answer as the nearest power
of .
 gatecse-2002 digital-logic number-representation normal descriptive

Answer key☟

6.24.23 Number Representation: GATE CSE 2003 | Question: 9

Assuming all numbers are in complement representation, which of the following numbers is divisible by
?

A. B. C. D.

gatecse-2003 digital-logic number-representation normal

Answer key☟

6.24.24 Number Representation: GATE CSE 2004 | Question: 19

If (in base-x number system) is equal to (in base -number system), the possible values of and
are

A. B. C. D.
gatecse-2004 digital-logic number-representation easy

Answer key☟

6.24.25 Number Representation: GATE CSE 2004 | Question: 28

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with
rounding?

A. and respectively B. and respectively

C. and respectively D. and respectively
gatecse-2004 digital-logic number-representation normal

Answer key☟

6.24.26 Number Representation: GATE CSE 2004 | Question: 66

Let and be two complement numbers. Their product in

complement is

A. B. C. D.
gatecse-2004 digital-logic number-representation easy

Answer key☟

6.24.27 Number Representation: GATE CSE 2005 | Question: 16, ISRO2009-18, ISRO2015-2

The range of integers that can be represented by an bit complement number system is:

A. B.
C. D.
gatecse-2005 digital-logic number-representation easy isro2009 isro2015

Answer key☟

6.24.28 Number Representation: GATE CSE 2005 | Question: 17

The hexadecimal representation of (657)8 is:

A. B. C. D.
 gatecse-2005 digital-logic number-representation easy

Answer key☟

6.24.29 Number Representation: GATE CSE 2006 | Question: 39

We consider the addition of two complement numbers and . A binary

adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by
and the carry-out by . Which one of the following options correctly identifies the overflow
condition?

A. B.
C. D.
gatecse-2006 digital-logic number-representation normal

Answer key☟

6.24.30 Number Representation: GATE CSE 2006 | Question: 40

Consider numbers represented in 4-bit Gray code. Let be the Gray code representation of a
number and let be the Gray code of value of the number. Which one of
the following functions is correct?

A.
B.
C.
D.

gatecse-2006 digital-logic number-representation binary-codes normal

Answer key☟

6.24.31 Number Representation: GATE CSE 2008 | Question: 6

Let denote number system radix. The only value(s) of that satisfy the equation is/are

A. decimal B. decimal C. decimal and D. any value

gatecse-2008 digital-logic number-representation normal

Answer key☟

6.24.32 Number Representation: GATE CSE 2009 | Question: 5, ISRO2017-57

is equivalent to

A. B. C. D.
gatecse-2009 digital-logic number-representation isro2017

Answer key☟

6.24.33 Number Representation: GATE CSE 2010 | Question: 8

is a -bit signed integer. The 's complement representation of is . The 's complement
representation of is

A. B. C. D.
gatecse-2010 digital-logic number-representation normal

Answer key☟

6.24.34 Number Representation: GATE CSE 2013 | Question: 4

The smallest integer that can be represented by an number in complement form is

A. B. C. D.
 gatecse-2013 digital-logic number-representation easy

Answer key☟

6.24.35 Number Representation: GATE CSE 2014 Set 1 | Question: 8

The base (or radix) of the number system such that the following equation holds is____________.

gatecse-2014-set1 digital-logic number-representation numerical-answers normal

Answer key☟

6.24.36 Number Representation: GATE CSE 2014 Set 2 | Question: 8

Consider the equation with and as unknown. The number of possible solutions is
_____ .

gatecse-2014-set2 digital-logic number-representation numerical-answers normal

Answer key☟

6.24.37 Number Representation: GATE CSE 2015 Set 3 | Question: 35

Consider the equation where and are unknown. The number of possible solutions is
_____

gatecse-2015-set3 digital-logic number-representation normal numerical-answers

Answer key☟

6.24.38 Number Representation: GATE CSE 2016 Set 1 | Question: 07

The complement representation of an integer is its decimal

representation is ____________

gatecse-2016-set1 digital-logic number-representation normal numerical-answers

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6.24.39 Number Representation: GATE CSE 2016 Set 2 | Question: 09

Let be the number of distinct -bit integers in complement representation. Let be the number of
distinct -bit integers in sign magnitude representation Then is______.

gatecse-2016-set2 digital-logic number-representation normal numerical-answers

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6.24.40 Number Representation: GATE CSE 2017 Set 1 | Question: 9

When two numbers and in 's complement representation (with and as

the least significant bits) are added using a ripple-carry adder, the sum bits obtained are and the
carry bits are . An overflow is said to have occurred if

A. the carry bit is

B. all the carry bits are
C. is

D. is

gatecse-2017-set1 digital-logic number-representation

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6.24.41 Number Representation: GATE CSE 2017 Set 2 | Question: 1

The representation of the value of a unsigned integer in hexadecimal number system is .

The representation of the value of in octal number system is

A. B. C. D.
gatecse-2017-set2 digital-logic number-representation

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6.24.42 Number Representation: GATE CSE 2019 | Question: 22

Two numbers are chosen independently and uniformly at random from the set
The probability (rounded off to decimal places) that their (unsigned) binary representations have the
same most significant bit is ___________.

gatecse-2019 numerical-answers digital-logic number-representation probability 1-mark

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6.24.43 Number Representation: GATE CSE 2019 | Question: 4

In -bit ’s complement representation, the decimal number is:

A. B.
C. D.
gatecse-2019 digital-logic number-representation 1-mark

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6.24.44 Number Representation: GATE CSE 2019 | Question: 8

Consider where and Z are all in sign-magnitude form. X and Y are each represented in
bits. To avoid overflow, the representation of would require a minimum of:

A. bits B. bits C. bits D. bits

gatecse-2019 digital-logic number-representation 1-mark

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6.24.45 Number Representation: GATE CSE 2021 Set 1 | Question: 6

Let the representation of a number in base be . What is the hexadecimal representation of the
number?

A. B. C. D.
gatecse-2021-set1 digital-logic number-representation normal 1-mark

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6.24.46 Number Representation: GATE CSE 2021 Set 2 | Question: 18

If and are two decimal digits and , the decimal value of is ___________

gatecse-2021-set2 numerical-answers digital-logic number-representation 1-mark

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6.24.47 Number Representation: GATE CSE 2021 Set 2 | Question: 44

If the numerical value of a -byte unsigned integer on a little endian computer is more than that on a big
endian computer, which of the following choices represent(s) the unsigned integer on a little endian
computer?

A. B. C. D.
gatecse-2021-set2 multiple-selects digital-logic number-representation little-endian-big-endian 2-marks

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6.24.48 Number Representation: GATE CSE 2022 | Question: 8

Let and be two registers that store numbers in complement form. For the operation
which one of the following values of and gives an arithmetic overflow?

A. and B. and
C. and D. and
gatecse-2022 digital-logic number-representation 1-mark

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6.24.49 Number Representation: GATE CSE 2023 | Question: 22

A particular number is written as in radix- representation. The same number in radix- representation
is _____________.

gatecse-2023 digital-logic number-representation numerical-answers 1-mark

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6.24.50 Number Representation: GATE CSE 2024 | Set 1 | Question: 3

Consider a system that uses bits for representing signed integers in 's complement format. In this
system, two integers and are represented as = and = . Which one of the following
operations will result in either an arithmetic overflow or an arithmetic underflow?

A. B. C. D.
gatecse2024-set1 digital-logic number-representation

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6.24.51 Number Representation: GATE CSE 2024 | Set 2 | Question: 39

Which of the following is/are EQUAL to in radix - (i.e., base - ) notation?

A. in radix -10 B. in radix -8

C. in radix -16 D. in radix -7
gatecse2024-set2 digital-logic number-representation multiple-selects

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6.24.52 Number Representation: GATE IT 2004 | Question: 42

Using a complement arithmetic, which of the following additions will result in an overflow?

i.
ii.
iii.

A. i only B. ii only C. iii only D. i and iii only

gateit-2004 digital-logic number-representation normal

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6.24.53 Number Representation: GATE IT 2004 | Question: 43

The number is equivalent to

A. and B. and
C. and D. and
gateit-2004 digital-logic number-representation normal

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6.24.54 Number Representation: GATE IT 2005 | Question: 47

evaluates to
 A. B. C. D. None of these
gateit-2005 digital-logic number-representation normal

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6.24.55 Number Representation: GATE IT 2006 | Question: 7, ISRO2009-41

The addition of , two's complement, binary numbers and results in

A. and an overflow B. and no overflow

C. and no overflow D. and an overflow
gateit-2006 digital-logic number-representation normal isro2009

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6.24.56 Number Representation: GATE IT 2007 | Question: 42

A. B.
C. D.
gateit-2007 digital-logic number-representation normal

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6.24.57 Number Representation: GATE IT 2008 | Question: 15

A processor that has the carry, overflow and sign flag bits as part of its program status word (PSW) performs
addition of the following two complement numbers and . After the execution of this
addition operation, the status of the carry, overflow and sign flags, respectively will be:

A. B. C. D.
gateit-2008 digital-logic number-representation normal

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6.25 Prime Implicants (2)

6.25.1 Prime Implicants: GATE CSE 1997 | Question: 5.1

Let be a switching function. Which one of the following is valid?

A. is a prime implicant of B. is a minterm of

C. is an implicant of D. is a prime implicant of
gate1997 digital-logic normal prime-implicants

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6.25.2 Prime Implicants: GATE CSE 2004 | Question: 59

Which are the essential prime implicants of the following Boolean function?

A. and B. and C. only. D. and

gatecse-2004 digital-logic normal prime-implicants

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6.26 ROM (4)

6.26.1 ROM: GATE CSE 1993 | Question: 6.6

A ROM is used to store the Truth table for binary multiple units that will multiply two -bit numbers. The size
of the ROM (number of words number of bits) that is required to accommodate the Truth table is
. Write the values of and .
 gate1993 digital-logic normal rom descriptive

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6.26.2 ROM: GATE CSE 1996 | Question: 1.21

A ROM is used to store the table for multiplication of two -bit unsigned integers. The size of ROM required
is

A. B.
C. D.
gate1996 digital-logic normal rom

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6.26.3 ROM: GATE CSE 2012 | Question: 19

The amount of ROM needed to implement a multiplier is

A. bits B. bits C. Kbits D. Kbits

gatecse-2012 digital-logic normal rom

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6.26.4 ROM: GATE IT 2004 | Question: 10

What is the minimum size of ROM required to store the complete truth table of an
multiplier?

A. bits B. bits
C. bits D. bits
gateit-2004 digital-logic normal rom

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6.27 Shift Registers (2)

6.27.1 Shift Registers: GATE CSE 1987 | Question: 13-a

The below figure shows four -type flip-flops connected as a shift register using a gate. The initial
state and three subsequent states for three clock pulses are also given.

The state after the fourth clock pulse is

A. B. C. D.
gate1987 digital-logic circuit-output sequential-circuit digital-counter shift-registers

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 6.27.2 Shift Registers: GATE CSE 1991 | Question: 06,a

Using flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the
following input lines:

i. Clock
ii. Three parallel data inputs
iii. Serial input

iv. Control input .

gate1991 digital-logic difficult sequential-circuit flip-flop shift-registers descriptive

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6.28 Static Hazard (1)

6.28.1 Static Hazard: GATE CSE 2006 | Question: 38

Consider a Boolean function . Suppose that exactly one of its inputs is allowed to change at a
time. If the function happens to be true for two input vectors and
, we would like the function to remain true as the input changes from to ( and differ
in exactly one bit position) without becoming false momentarily. Let
. Which of the following cube covers of will ensure that the required
property is satisfied?

A.
B.
C.
D.

gatecse-2006 digital-logic min-sum-of-products-form difficult static-hazard

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6.29 Synchronous Asynchronous Circuits (4)

6.29.1 Synchronous Asynchronous Circuits: GATE CSE 1991 | Question: 03-ii

Advantage of synchronous sequential circuits over asynchronous ones is:

A. faster operation B. ease of avoiding problems due to

hazards
C. lower hardware requirement D. better noise immunity
E. none of the above
gate1991 digital-logic normal sequential-circuit synchronous-asynchronous-circuits multiple-selects

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6.29.2 Synchronous Asynchronous Circuits: GATE CSE 1998 | Question: 16

Design a synchronous counter to go through the following states:

gate1998 digital-logic normal descriptive synchronous-asynchronous-circuits

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6.29.3 Synchronous Asynchronous Circuits: GATE CSE 2001 | Question: 2.12

Consider the circuit given below with initial state . The state of the circuit is given by
the value
 Which one of the following is correct state sequence of the circuit?

A. B.
C. D.
gatecse-2001 digital-logic normal synchronous-asynchronous-circuits

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6.29.4 Synchronous Asynchronous Circuits: GATE CSE 2003 | Question: 44

A , synchronous sequential circuit behaves as follows:

Let denote the number of and respectively in initial bits of the input
. The circuit outputs until one of the following conditions holds.

. In this case, the output at the k-th and all subsequent clock ticks is .
. In this case, the output at the k-th and all subsequent clock ticks is .

What is the minimum number of states required in the state transition graph of the above circuit?

A. B. C. D.
gatecse-2003 digital-logic synchronous-asynchronous-circuits normal

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Answer Keys
6.1.1 N/A 6.1.2 N/A 6.1.3 B 6.1.4 B 6.1.5 A
6.1.6 B 6.1.7 19.2 6.1.8 B 6.1.9 -1 6.2.1 B
6.2.2 C 6.3.1 D 6.3.2 C 6.3.3 N/A 6.3.4 N/A
6.3.5 N/A 6.3.6 D 6.3.7 N/A 6.3.8 A 6.3.9 B
6.3.10 D 6.3.11 C 6.3.12 D 6.3.13 C 6.3.14 C
6.3.15 D 6.3.16 D 6.3.17 D 6.3.18 A 6.3.19 A
6.3.20 D 6.3.21 D 6.3.22 D 6.3.23 1 6.3.24 A
6.3.25 C 6.3.26 C 6.3.27 D 6.3.28 B 6.3.29 B;C;D
6.3.30 B;C 6.3.31 B 6.3.32 C 6.4.1 N/A 6.4.2 A
6.4.3 B 6.4.4 A 6.4.5 C 6.4.6 B 6.5.1 A
6.5.2 A 6.5.3 C 6.5.4 A 6.5.5 3 6.5.6 A
6.5.7 3 6.5.8 B 6.5.9 C;D 6.6.1 A 6.6.2 B
6.7.1 B 6.7.2 N/A 6.7.3 C 6.7.4 N/A 6.7.5 N/A
6.7.6 A;C 6.7.7 B 6.7.8 B 6.7.9 B 6.7.10 011
6.7.11 D 6.7.12 C 6.7.13 N/A 6.7.14 N/A 6.7.15 B
6.7.16 B 6.7.17 A 6.7.18 A 6.7.19 A 6.7.20 D
6.7.21 A 6.7.22 A 6.7.23 D 6.7.24 A 6.7.25 C
6.7.26 C 6.7.27 C 6.7.28 A 6.7.29 A 6.7.30 B
6.7.31 D 6.7.32 B 6.7.33 C 6.7.34 C 6.7.35 X