EE1373 – Digital Logic Circuits Department of EEE/EIE 2022-2023

UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES

PART-A (C206.1)
1. How many bits are required to represent the decimal numbers in the
range 0 to 999 using Straight binary codes and using BCD codes?
2n= maximum value with n bits
29=512; 210=1024;
So to represent decimal number in the range 0 to 999 using straight binary
code, 10 bits are required.
In BCD Code - 1 decimal digit requires 4 bits.
So to represent decimal number in the range 0 to 999 using BCD code (3
digits), 12 bits are required.
2. Show that the excess-3 code is self-complementing.
Self-complementing property: 1’s complement of Excess 3 code of a
decimal digit is equal to Excess-3 code of 9‘s complement of the
corresponding decimal digit.
Example:
a. Excess -3code of the decimal digit 2= 0101
b. 1‘s complement of 0101= 1010 --------------------(1)
c. 9‘s complement of 2 = 9-2 = 7
d. Excess -3 code of 7 = 1010 --------------------(2)
e. From (1) and (2), 1’s complement is equal to 9‘s complement
f. The self-complementing property of Excess -3 code is proved.
3. Determine (377)10 in Octal and Hexa-decimal equivalent. (Nov 2014)
8 377 16 377
8 47 1 16 23 9
5 7 1 7
(377)10 = (571)8 (377)10 = (179)16
4. Add the decimals 67and 78 using excess-3 code.
67 = (0110 0111 )BCD= (1001 1010)XS-3
78 = (0111 1000 )BCD= (1010 1011)XS-3
------------------------
0001 0100 0101 → (1)
After excess 3 addition, if carry is available after nibble, subtract 3 to the

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result,
Else if no carry after nibble, add 3 to the result.
From (1), no carry after each nibble, so adding 3 to each nibble.
(1) 0001 0100 0101
0011(+) 0011(+) 0011(+)
-------------------------------
(0100 0111 1000)XS-3
5. Add the decimals 57and 68 using 8421 BCD code.
57 = (0101 0111 )
68 = (0110 1000 )
--------------------------
1011 1111 → (1)
After BCD addition, if nibble is greater than 9, add 6, else if nibble is less
than 9, subtract 6 for each nibble.
From (1) each nibble is greater than 9, hence adding 6 to each nibble
(1) 1011 1111(+)
0110 0110
-------------------------------
(0001 0010 0101)
6. What is Gray code &mention the advantages and application of Gray
code (Nov 2017)
The gray code is non-weighted code, which means that there are no specific
weights assigned to the bit positions. In gray code, only one bit changes from
one number to the next.
Advantages of Gray Code:Switching activity is reduced because of one
digit change in consequence code words.
Low power consumption, Fast response & Minimum error in coding are the
advantages of gray code.
Application:
Shaft position encoder in which analog data are represented by continuous
change of a shaft position. The shaft is partitioned into segments, and each
segment is assigned a number.

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7. Convert the following hexadecimal numbers into decimal numbers:263

and 1C3 (May2012)

263H= 2x162+6x161+3x160=(611)10

1C3H=1x162+12x161+3x160=(451)10
8. i) Convert (11001010)2 into gray code. ii) (11101101) gray code into
binary code. (Nov 2021)
(i) 11001010 to gray code
1+ 1+ 0 + 0 + 1 + 0 + 1+ 0

1 0 1 0 1 1 1 1
(11001010)2= (10101111)gray
(ii) 11101101 to binary
1 1 1 0 1 1 0 1

1 0 1 1 0 1 1 0
(11101101)gray= (10110110)2
9. Convert: a)(475.25)8to its decimal equivalent & b)(549.B4)16to its binary
equivalent (Apr 2015)
a) (475.25)8to its decimal equivalent
= 4 x 82 + 7 x 81 + 5 x 80 + 2 x 8-1 + 5 x 8-2
= 4 x 64 + 7 x 8 + 5 x 1 + 2 x 0.125 + 5 x 0.0156
=317.25
(475.25)8=(317.25)10
b) (549.B4)16to its binary equivalent
5 4 9 . B 4
0101 0100 1001 1011 0100
(549.B4)16 = (010101001001.10110100)2
10. What is unit distance code? Give an example. (Nov 2015)
Unit distance code is a non-weighted code in which next increment or
decrement causes the bit transition only at one place. Ex: Gray code.
11. Convert the following binary code into gray code 10101110002.
1+ 0+ 1 + 0 + 1 + 1 + 1+ 0+ 0+ 0

1 1 1 1 1 0 0 1 0 0
(1010111000)2= (1111100100)gray

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12. Convert (115)10 and (235)10 to hexadecimal numbers. (Nov 2017)

16 115 16 235
16 7 3 16 14 B
0 7 0 E
(115)10= (73)16 (235)10= (BE)16
13. Convert the following Excess 3 numbers into decimal numbers.
a) a) 1011 b) 1001 0011 0111
- 0011 - 0011 0011 0011
--------- --------------------------
1000 = (8)10 0100 0000 0100 = (404)10
14. Convert 14310 into its binary and binary coded decimal equivalent. (Apr
2017)
2 143
2 71 1
2 35 1
2 17 1
2 8 1
2 4 0
2 2 0
1 0
In binary, (143)10= (1000 1111)2
In BCD, (143)10= (0001 0100 0011)BCD
15. Perform subtraction on the following unsigned binary numbers using 2’s
complement of subtrahend (a) 11011- 11001 (b) 110100- 10101. (Nov
2019)
a) 11011- 11001
1’s complement of 11001 =00110
2’s Complement of 11001 = (1’s complement of 11001+1) =00111
Add 00111 with 11011
1111
11011
0 0 1 1 1 (+)
-----------
100010
Eliminate the carry
Ans =11011-11001 =00010

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b)110100- 10101
1’s complement of 010101 =101010
2’s Complement of 010101=101010+1=101011
Add 101011 with 110100
1 1 0 1 0 0 (+)
101011
----------------
1011111
Eliminate Carry
Ans = 011111
16. Convert (101.01)2 to decimal number. (April 2019)
(101.01)2 = [(1 × 22) + (0 × 21) + (1 × 20) + (0 × 2–1) + (1 × 2–2)]10
= 5.2510.
17. Give each one example for error detecting code and error correcting
code. (April 2019)
Error detection codes
Error Correction codes are used to detect the errors present in the received
data bit stream. These codes contains some parity bits which are appended to
the original data bit stream. These codes detect the error, if it is occurred
during transmission of the original data bit stream.
Examples: Parity code, Hamming code.
Error correction codes-
Error correction Codes are used to correct the errors present in the received
data bit stream. Error correction codes also use the similar strategy of error
detection codes.
Example − Hamming code.
18. A16-bit data word given by 1001100001110110 is to be transmitted by
using a fourfold repetition code. If the data word is broken into four
blocks of four bits each, then write the transmitted bitstream. (Nov/ Dec
2020: May 2021)
A 16-bit data word given by 1001100001110110 is to be transmitted by using
a fourfold repetition code. If the data word is broken into four blocks of four
bits each, then the transmitted bit stream is 1001 1001 1001 1001 1000 1000
1000 1000 0111 0111 0111 0111 0110 0110 0110 0110

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19. Give the classification of logic families.

The classifications of logic families are
(i) Saturated Logic Family (ii)Non Saturated Logic Family
S.No Saturated Logic Family Non-Saturated Logic Family
1) Register Transistor Logic(RTL) 1)Schottky TTL
2) Diode Transistor Logic (DTL) 2)Emitter Coupled Logic(ECL)
3) Transistor Transistor Logic (TTL)

20. Define Fan- In and Fan-Out? (Nov 2015)(May 2016)

Fan- In is the number of inputs connected to the gate without any degradation
in the voltage level. Fan-Out is defined as the maximum number of inputs of
several gates that can be driven by the output of logic gate maintaining its
output levels within the specified limits.
21. Define power dissipation and noise margin?
Power dissipation is measure of power consumed by the gate when fully
driven by all its inputs. It is the maximum noise voltage added to an input
signal of a digital circuit that does not cause an undesirable change in the
circuit output. It is expressed in volts.
22. What is the advantages of ECL over TTL? (Nov 2014) (Nov 2021)
Transistors in ECL logic families do not saturate which eliminates the storage
time delay. So ECL families have the fastest operating speed and the
propagation delay time per gate is approximately 1ns while that of TTL is 12 ns.
23. Compare the totem pole output with open collector output. (Nov 2014)
Totem pole Open collector
Output stage consists of Pull up
Output stage consists of only pull
transistor, Diode resistor and pull - down
down transistor.
transistor.
External pull-up resistor is required
External pull-up resistor is not Required.
for proper operation of gate
Output of two gates can be tied
Output of two gates cannot be tied
together using wired AND
together.
technique.
Operating speed is high. Operating speed is low.
24. List the different types of output configuration in TTL (Nov 2019)
There are three different types of output configuration in TTL .They are
(i) Totem pole configuration

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(ii) Open Collector configuration

Tristate configuration
25. Draw the circuit diagram of standard TTL NAND gate. (Nov/ Dec 2020:
May 2021).

TTL based NAND gate

PART-B (C201.1)
1. (i) A 12 bit hamming code word containing 8 bits of data and 4 parity
bits is read from memory. What was the original 8 bit data word
that was written into memory if the 12 bit word read out is as (1)
101110010100 and (2) 111111110100.
Step 1:Construct bit location table

Step 2: Check for even parity bits

For P1:
P1 checks locations 1, 3, 5, 7, 9 ,11 = 1,1,1,0,0,0
There are three 1s in the group
Hence Parity check for even parity is wrong……………….….….1 (LSB)
For P2:
P2 checks locations 2,3, 6 ,7 ,10 =0,1,0,0,1
There are two 1s in the group
Hence Parity check for even parity is correct…………………….…….0
For P4:
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P4 checks locations 4, 5, 6, 7, 12 = 1,1,0,0,0

There are two 1s in the group
Hence Parity check for even parity is correct…….…………………….0
For P8:
P8 checks locations 8, 9, 10, 11, 12 = 1,0,1,0,0
There are two 1s in the group
Hence Parity check for even parity is correct ……………….…….0 (MSB)
The resultant word is 0001
The bit position 1 in the error.The corrected code is 001110010100.
Actual data transmitted :11000100.
(2) Received 12 bit code : 111111110100

Step 2: Check for even parity bits

For P1:
P1 checks locations 1, 3, 5, 7, 9 ,11 = 1,1,1,1,0,0
There are four 1s in the group
Hence Parity check for even parity is correct……………….….….0 (LSB)
For P2:
P2 checks locations 2,3, 6 ,7 ,10 =1,1,1,1,1
There are five 1s in the group
Hence Parity check for even parity is wrong…………………….…….1
For P4:
P4 checks locations 4, 5, 6, 7, 12 = 1,1,1,1,0
There are four 1s in the group
Hence Parity check for even parity is correct…….…………………….0
For P8:
P8 checks locations 8, 9, 10, 11, 12 = 1,0,1,0,0

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There are two1s in the group

Hence Parity check for even parity is correct ……………….…….0 (MSB)
The resultant word is 0010
The bit position 2 in the error. The corrected code is 101111110100
Actual data transmitted :11110100
(ii) Briefly discuss weighted binary code.(Nov2015)
Weighted codes:
• In weighted codes, each digit is assigned a specific weight according to
its position.
• For example, in 8421 BCD code, 1001 the weights of 1, 0, 0, 1 (from left
to right) are 8, 4, 2 and 1 respectively.
• Suppose W1 W2 W3 and W4 are the weights of binary digits and Xl X2
X3 and X4 are the corresponding digit values then decimal digit.
• N = W1 Xl + W2 X2 + W3 X3 + W4 X4 is represented by binary
sequence X4 X3 X2 X4.
• The codes 8421 BCD, 2421 BCD, 5211 BCD are all weighted codes.

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2. (i) State the differences between 1’s complement and 2’s

complement subtraction with suitable examples.
Steps for 1’s Complement Subtraction:
Subtraction of Smaller Number from Larger Number:
The steps for 1’s complement subtraction of a smaller number from a larger
binary number are as follows:
Step-1: Determine the 1’s complement of the smaller number.
Step-2: Add this to the larger number.
Step-3: Remove the carry and add it to the result. This carry is called end-
around-carry.
Example-1: Subtract (1010)2 from (1111)2 using 1’s complement method.
Step-1: Find the 1’s complement of 1010. It will be found by replacing all 0
to 1 and all 1 to 0. In this way, the required 1’s complement will be 0101.
Step-2: In this step, we need to add the vale calculated in step-1 to 1111.
This is shown below.

Subtraction of Larger Number from Smaller Number:

The steps involved in 1’s complement subtraction of a larger number from a
smaller number are as follows:
Step-1: Determine the 1’s complement of the larger number.
Step-2: Add this to the smaller number.
Step-3: The answer is the 1’s complement of the true result and opposite in
sign. There is no carry.
Example: Subtract (1010)2 from (1000)2 using 1’s complement method.
The 1’s complement of (1010)2 is (0101)2. Now, we will add this with the
smaller number and finally take 1’s complement of the result to get the
answer. This is shown below.

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Steps for 2’s Complement Subtraction:
Subtraction of Smaller Number from Larger Number:
To subtract a smaller number from a larger number using 2’s complement
subtraction, following steps are to be followed:
Step-1: Determine the 2’s complement of the smaller number
Step-2: Add this to the larger number.
Step-3: Omit the carry. Note that, there is always a carry in this case.
Following example illustrate the above mentioned steps:
Exampe-1: Subtract (1010)2 from (1111)2 using 2’s complement method.
Solution:
Step-1: 2’s complement of (1010)2 is (0110)2.
Step-2: Add (0110)2 to (1111)2. This is shown below.

Subtraction of Larger Number from Smaller Number:

To subtract a larger number from a smaller number using 2’s complement
subtraction, following steps are to be followed:
Step-1: Determine the 2’s complement of the smaller number
Step-2: Add this to the larger number.
Step-3: There is no carry in this case. The result is in 2’s complement form
and is negative.
Step-4: To get answer in true form, take 2’s complement and change its
sign.
Example-2: Subtract (1010)2 from (1000)2 using 2’s complement.
Solution:
Step-1: Find the 2’s complement of (1010)2. It is (0110)2.
Step-2: Add (0110)2 to (1000)2

(ii) Explain about error detection and correction codes.(Nov 2017)

In digital communication system errors are transferred from one
communication system to another, along with the data. If these errors are

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not detected and corrected, data will be lost .Error detection is the process
of detecting the errors that are present in the data transmitted from
transmitter to receiver, in a communication system

Parity Checking

Parity bit is used for detecting errors during the transmission of binary
information. Parity bit is an extra bit included with a binary message to make
the number of 1’s either even or odd. This message including the parity pit is
transmitted and checked at the receiving end for error. The circuit that
generate the parity bit in the transmission is called parity generator. The
circuit that checks the parity in the receiver is called parity checker.

Even Parity

•If the added parity bit makes number of 1’s as even , then it is called as Even
parity

Ex: data is 10000001 -> parity bit 0

• If the data has odd number of 1’s, the parity bit is 1.

Ex: data is 10010001 -> parity bit 1

Odd Parity

If the added parity bit makes number of 1’s as odd, then it is called as odd
parity.

• If the data has odd number of 1’s, the parity bit is 0.

Ex: data is 10011101 -> parity bit 0

• Even number of 1’s, the parity bit is 1. Ex: data is 10010101 -> parity bit 1

Error Correcting Codes

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The codes which are used for both error detecting and error correction are
called as “Error Correction Codes”. Hamming code is an example of error
detecting and correcting code.

Hamming Code :The error detecting and correcting code technique is

developed by R.W.Hamming . Hamming code not only identifies the error
bit, in the whole data sequence but also corrects it. This code uses a number
of parity bits located at certain positions in the code word. The number of
parity bits depends upon the number of information bits. Hamming code is
used for single error detection.
3. (i) Convert 10101110111011002 into its octal, decimal and
hexadecimal equivalent.
Binary to octal conversion
Group by 3 to convert to octal
001 010 111 011 101 1002
1 2 7 3 5 4

Answer = (127354)8

Group by 4 to convert to hexadecimal

1010 1110 1110 1100

A E E C

(1010111011101100)2= (AEEC)16

Decimal

(1010111011101100)2=1*215+0*214+1*213+0*212+1*211+1*210+1*29+0*28
+1*27+1*26+1*25+0*24+1*23+1*22+0*21+0*20

=32768+8192+2048+1024+512+128+64+32+8+4

(1010111011101100)2= (44780)10

(ii) Deduce the odd parity hamming code for the data: 1010.
Introduce an error in the LSB of the hamming code and
deduce the steps to detect the error. (May 2016)
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P1 checks bits positions 1, 3, 5 and 7 =P1,1,0,1

For odd parity P1=1
P2 checks bits positions 2,3, 6 and 7 =P2,1,1,1
For odd parity P2=0
P3 checks bits positions 4,5, 6 and 7 = P3, 0,1,1
For odd parity P3=1
Hamming code = 0110010
Introduce an error in the LSB of the hamming code : 0110010

P1 checks bits positions 1, 3, 5 and 7 =1,1,0,0

There are two 1’s , hence odd parity is wrong ------ 1 (LSB)
P2 checks bits positions 2,3, 6 and 7 =1,1,1,0
There are three 1’s hence odd parity is correct -----0
P3 checks bits positions 4,5, 6 and 7 = 0, 0,1,0
Odd parity is correct --------------------------------0 (MSB)
The code is 001 .the bit position 1 is having error
The corrected code is 0110010
4. (i) Perform the following addition using BCD and Excess-3 addition
(205+569).
BCD number of 205 = 0010 0000 0101
BCD number of 569= 0101 0110 1001 (+)
---------------------------
0111 0110 1110

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0110 (+)
---------------------------
0111 0111 0100
-----------------------------
Answer =774
Excess 3 Addition
Excess 3 code of 205 = 0101 0011 1000
Excess 3 code of 569 =1000 1001 1100 (+)
---------------------------------------------------
1101 1101 0100
Now add 0011 to the group which produce the carry and subtract 0011 from
group which do not produce carry
Ans : 1101 1101 0100
0011(-) 0011 (-) 0011(+)
------------------------------
1010 1010 0111
---------------------------

(ii) Encode the following binary word 1011into seven bit even parity
hamming code. (Apr2015)
If the number of data bits is designated as d, then the number of parity bit p
can be found by the following relationship,
• 2p ≥ d + p +1
Here d=4 , let p=3
23 = 4+3+1=8

P1 checks bits positions 1, 3, 5 and 7 =P1,1,0,1

For even parity P1=0

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P2 checks bits positions 2,3, 6 and 7 =P2,1,1,1

For even parity P2 =1
P3 checks bits positions 4,5, 6 and 7 = P3, 0,1,1
For Even Parity P3 =0

Hamming code is 0110011

5. (i) Explain in detail the usage of hamming codes for error
detection and error correction with an example considering
the data bits as 0101.
If the number of data bits is designated as d, then the number of parity bit p
can be found by the following relationship,
• 2p ≥ d + p +1
Here d=4 , let p=3
23 = 4+3+1=8
Consider Even parity

P1 checks bits positions 1, 3, 5 and 7 = P1,0,1,1

For even parity P1=0
P2 checks bits positions 2,3, 6 and 7 = P2,0,0,1
For even parity P2 =1
P3 checks bits positions 4,5, 6 and 7 = P3, 1,0,1
For even parity P3 =0

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Hamming code is 0100101

Introducing error in bit 2

Check for even parity

P1 checks bits positions 1, 3, 5 and 7 =0,0,1,1
Even parity is correct-----------------------------------0 (LSB)
P2 checks bits positions 2,3, 6 and 7 =0,0,0,1
Even parity fails -----------------------------------1
P3 checks bits positions 4,5, 6 and 7 =0,1,0,1
Even parity is correct-----------------------------------0 (MSB)
Error bit position is 010 . The bit position 2 has an error .
The corrected code is 0100101
(ii) Convert FACE16 into its binary octal and decimal equivalent.
(Apr 2017) (Nov 2021)
FACE = (15*163)+(10*162)+( 12*161)+( 14*160)

= 61440+2560+192+14= (64206)10

FACE to binary

F A C E

1111 1010 1100 1110

FACE = (1111 1010 1100 1110)2

FACE to Octal

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001 111 101 011 001 110

1 7 5 3 1 6

FACE =(175316)8

6. Explain the basic working principles of following digital logic families.

(i) TTL (ii) ECL and (iii) CMOS(May2013) (Nov 2019)

The diodes D2 and D3 represents the two E-B junction of Q1 and D4 is the
collector-base(CB) junction.
• The input voltages A and B are either LOW (ideally grounded) or HIGH (ideally
+5 volts).
• If either A and B or both are low, the corresponding diode conducts and the base
of Q1 is pulled to approximately 0.7V. This reduces the base voltage of Q2 to
atmost zero. Therefore, Q2 cuts off. With Q2 open, Q4 goes into cut-off and the Q3
Base is pulled HIGH. Since Q3 acts as an emitter follower, the Y output is pulled
up to a HIGH voltage.
• On the other hand, when A and B both are HIGH, the emitter diode of Q1 is
reverse biased making them off. This causes the collector diode D4 to get in to
forward conduction. This forces Q2 base to go HIGH. In turn, Q4 goes into
saturation, producing a low output in all input and output conditions.
• Without diode D1 in the circuit, Q3 will conduct slightly when the output is low.
• To prevent this, the diode is inserted. Its voltage drops keeps the base-emitter
diode of Q3 reverse biased.
• In this way, only Q4 conducts when the output is low.
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Basic ECL Circuit:

The basic inverter/buffer circuit in ECL family consists of two transistor connected
in differential single ended input mode with a common emitter resistance.

The circuit has two outputs: inverting output (OUT1) and non-inverting output
(OUT2). For this circuit, the input LOW and HIGH voltage levels are defined as
3.6 V and 4.4 V, and it produces output LOW and HIGH levels as 4.2 V and 5.0 V.
• When VIN is HIGH (4.4V), transistor Q1 is ON, but not saturated and transistor
Q2 is OFF. Thus VOUT2 is pulled to 5.0V (HIGH) through R2 and drop across R1 is
0.8 V so that VOUT1.
• When VIN is LOW (3.6V), transistor Q2 is ON, but not saturated and transistor
Q1 is OFF. Thus, VOUT1 is pulled to 5.0V (HIGH) through R1 and drop across R2
is 0.8 V so that VOUT2 is 4.2 V (LOW).
CMOS Inverter:
• It consists of two MOSFET’s in series in such a way that the p-channel device
has its source connected to +VDD and the n-channel device has its source connected
to ground.
• The gates of the two devices are connected together as the common input and the
drains are connected together as the common output. 1. When input is HIGH, the
gate of Q1 (p=channel) is at 0 V relative to the source of Q1 i.e. Vgs1 = 0 V. Thus

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Q1 is OFF. On the other hand, the gate of Q2 (n-channel) is at +VDD relative to its
source i.e. Vgs2 = +VDD. Thus, Q2 is ON. This will produce VOUT = 0 V .
When input is LOW, the gate of Q1 (p=channel) is at negative potential relative to
its source while Q2 has Vgs = 0 V. Thus Q1 is ON and Q2 is OFF. This produces
output voltage approximately +VDD .

7. Explain the characteristics and implementation of the given digital logic

families: (i) DTL and (ii) RTL (Apr 2018)

The DTL circuit combines the diode AND gate and the bipolar transistor
inverter into a NAND gate. The AND function is performed by two diodes
with a resistor for pull up and NOT function is formed by the transistor inverter
circuit.
• When A=0, B=0, the node X has 0V. This 0V is given as an input to the

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transistor Q1. The transistor will be in cut off condition only. Node C will have
+5V (HIGH).
• Similarly if any one input is 0, A=0, B=0 or both A and B are 0, then the
node X will be grounded. Hence there is no base current. The transistor will
be in cut off condition. Therefore the node C will have +5V (HIGH).
• But for the inputs A=1, B=1, A and B are give +5V. Now the node X will
have +5V (since both diodes do not conduct). This voltage is given to the
transistor’s base with a drop by R2. • Now the transistor conducts. The output
of the NAND gate is LOW. The node C is grounded.
Characteristics oF DTL
1.Noise margin is high
2.Fan-in is of 8
3.A fan-out as high as 8 is possible for the DTL family because of high input
impedance
4.The turn-off delay is considerably larger than turnon delay by a factor of 2
or 3.The propogation delay is 25 ns
RTL working:

• When inputs A, B are ‘0’, the transistors Q1 and Q2 are OFF. Thus the node
C is not connected to ground and the Vcc will appear at node C s output which
is logic ‘1’.
• When any one inputs either A or B is ‘1’ or if both A and B are ‘1’ Q1 or Q2
or both the transistors will be in saturated mode. Thus the node C will be
connected to ground making the output C as 0V or Logic LOW for all the

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remaining three conditions.

Characteristics of RTL logic circuit:
1. Speed of operation is low. The propagation delay is in the order of 500ns. It
cannot operate at speeds above 4MHz.
2. Fan out is 4 or 5 with a switching delay of 50ns and fan in is 4.
3. Poor noise immunity.
4. High average power dissipation due to resistors.
5. The noise margin from zero to the threshold voltage is about 0.5V and from
one to the threshold voltage is 0.2V.
6. Sensitive to temperature. The RTL family of ICs includes NOR gates, flip
flops and 4 bit shift registers.
8. With circuit schematic, Explain the operation of a two input TTL NAND
gate with totem pole output. (Nov 2018) (Nov 2021)
2-Input TTL NAND Gates
• The circuit diagram of 2-input TTL NAND Gate is as shown in
figure.

• Its input structure consists of multiple-emitter transistor and output

structure consists of totem-pole output. Here, Q1 is an NPN transistor
having two emitters, one for each input to the gate.
• Although this circuits looks complex, we can simplify its analysis by using
the diode equivalent of the multiple-emitter transistor Q1
The diodes D2 and D3 represents the two E-B junction of Q1 and D4 is the
collector-base(CB) junction.

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• The input voltages A and B are either LOW (ideally grounded) or HIGH
(ideally +5 volts).
• If either A and B or both are low, the corresponding diode conducts and
the base of Q1 is pulled to approximately 0.7V. This reduces the base
voltage of Q2 to atmost zero. Therefore, Q2 cuts off. With Q2 open, Q4
goes into cut-off and the Q3 Base is pulled HIGH. Since Q3 acts as an
emitter follower, the Y output is pulled up to a HIGH voltage.
• On the other hand, when A and B both are HIGH, the emitter diode of Q1
is reverse biased making them off. This causes the collector diode D4 to get
in to forward conduction. This forces Q2 base to go HIGH. In turn, Q4 goes
into saturation, producing a low output in all input and output conditions.
• Without diode D1 in the circuit, Q3 will conduct slightly when the output
is low.
• To prevent this, the diode is inserted. Its voltage drops keeps the base-
emitter diode of Q3 reverse biased.
• In this way, only Q4 conducts when the output is low.

Compare totem pole and open collector outputs. (Apr 2017) (Nov 2021)
Totem pole output Open collector output
Output stage consists of pull
up transistor (Q4), diode Output stage consists of only pull
resistor and pull down down transistor.
transistor (Q5).
External pull up resistor is not
External pull up resistor is
required for proper operation of
not required.
gate.
Output of two gates can be tied
Output of two gates cannot
together using Wired AND
be tied together.
technique.
Operating speed is high. Operating speed is low.
9. Explain with an aid of circuit diagram the operation of 2 input CMOS

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NAND gate and list out its advantages over other logic families.
• It consists of two p-channel MOSFET’s Q1 and Q2, connected in parallel
and two n-channel MOSFET’s Q3 and Q4 connected in series.
When both the inputs are low, the gates of both p-channel MOSFET’s are
negative with respect to their source, since the sources are connected to
+VDD. Thus Q1 and Q2 are both ON. Since the gateto-source voltages of
Q3 and Q4 (n-channel MOSFETs) are both 0 V, those MOSFET’s are
OFF. The output is therefore connected to +VDD (HIGH) through Q1 and
Q2 and is disconnected from ground, as shown in fig(b).

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When A=0 and B=+VDD, Q1 is ON because Vgs1= -VDD and Q4 is ON

because Vgs4= +VDD. MOSFET’s Q2 and Q3 are OFF because their gate-
to-source voltages are 0 V. Since Q1 is ON and Q3 is OFF, the output is
connected to +VDD and it is disconnected from ground. Hence output is
HIGH.
When A=+VDD and B=0, Q1 is OFF because Vgs1=+VDD and Q4 is OFF
because Vgs4=-VDD. MOSFET’s Q2 and Q3 are ON because their gate-
to-source voltage is +VDD. Since Q2 and Q3 are ON, the output is
connected to +VDD and it is disconnected from ground. Output is HIGH.
Finally, when both inputs are HIGH, Q1 and Q2 are both OFF and Q3 and
Q4 are both ON, therefore the output is connected to ground and is LOW.
Note:
• P-channel MOSFET is ON when its gate voltage is negative with respect to
its source
• N-channel MOSFET is ON when its gate voltage is positive with respect to
its source.

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Given the two binary numbers X=1010100 and Y=1000011, perform the
subtraction Y-X using 2’s complements.(Nov 2016)
Y = 1000011
2’s Complement of X = (0101011+1)= 0101100 (+)
-------------------
1101111
There is no carry ,take 2’s complement of the result and negate
2’s complement of 1101111 =0010001
Answer = - 0010001
10. With circuit schematic and explain the operation and characteristics of
an ECL.
The circuit shown below represents the emitter-coupled logic circuit of an
inverter. It has two NPN transistors connected in differential single-ended
input mode.

Both the emitters are connected together with common resistance RE. The
resistor RE is a current limiting resistance and it prevents the transistor from
entering into saturation.It has two outputs: inverting output(VOUT1) and non-
inverting output(VOUT2). VIN is the input terminal, where LOW or HIGH input
is given.

When the input is HIGH, it will turn ON the transistor Q1 but not saturated
and the transistor Q2 is turned OFF. This will pull the output VOUT2 to HIGH

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but due to the drop in resistant R1, the output at terminal VOUT1 will be at LOW
value.

On the other side, when the input VIN is given LOW value, it will turn OFF the
transistor Q1 and the transistor is turned ON. The transistor Q2 will not enter
into saturation and it will make the output at terminal VOUT1 to be pulled HIGH
. Due to the drop in resistance R2, the output at terminal VOUT2 will have LOW
value.

Advantages

● High-speed operation is possible and so the fastest logic family.

● Since transistors are not allowed to enter into saturation, which reduces
the storage delay.
● Fan-out capability is high.
11. Design a CMOS inverter and explain its operation. Comment on its
characteristics such as Fan-in, Fan-out, power dissipation, propagation
delay and noise margin. Compare its advantages over other logic
families.(Apr 2017)
CMOS Inverter:
• It consists of two MOSFET’s in series in such a way that the p-channel
device has its source connected to +VDD and the n-channel device has its
source connected to ground.
• The gates of the two devices are connected together as the common input
and the drains are connected together as the common output. 1. When input is
HIGH, the gate of Q1 (p=channel) is at 0 V relative to the source of Q1 i.e.
Vgs1 = 0 V. Thus Q1 is OFF. On the other hand, the gate of Q2 (n-channel) as
at +VDD relative to its source i.e. Vgs2 = +VDD. Thus, Q2 is ON. This will
produce VOUT = 0 V as in figure. 2. When input is LOW, the gate of Q1
(p=channel) is at negative potential relative to its source while Q2 has Vgs =
0 V. Thus Q1 is ON and Q2 is OFF. This produces output voltage
approximately +VDD in figure.

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12. (i) Design a 3- input NAND gate circuit using TTL Logic.
3-Input TTL NAND Gate:
• The three inputs TTL NAND Gate is same as that of two input TTL
NAND Gate except that its Q1 (NPN) transistor has three emitters instead
of two. Rest of the circuit is same.
• For three input NAND gate if all the inputs are logic 1 then only output is
logic 0; otherwise output is logic 1. The operation is similar to the 2-input
NAND gate.

2-Input TTL NAND Gates

• The circuit diagram of 2-input TTL NAND Gate is as shown in figure.
• Its input structure consists of multiple-emitter transistor and output
structure consists of totem-pole output. Here, Q1 is an NPN transistor
having two emitters, one for each input to the gate.

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The diodes D2 and D3 represents the two E-B junction of Q1 and D4 is the
collector-base(CB) junction.
• The input voltages A and B are either LOW (ideally grounded) or HIGH
(ideally +5 volts).
• If either A and B or both are low, the corresponding diode conducts and
the base of Q1 is pulled to approximately 0.7V. This reduces the base
voltage of Q2 to atmost zero. Therefore, Q2 cuts off. With Q2 open, Q4
goes into cut-off and the Q3 Base is pulled HIGH. Since Q3 acts as an
emitter follower, the Y output is pulled up to a HIGH voltage. On the other
hand, when A and B both are HIGH, the emitter diode of Q1 is reverse
biased making them off. This causes the collector diode D4 to get in to
forward conduction. This forces Q2 base to go HIGH. In turn, Q4 goes into
saturation, producing a low output in all input and output conditions.
• Without diode D1 in the circuit, Q3 will conduct slightly when the output
is low. To prevent this, the diode is inserted. Its voltage drops keeps the
base-emitter diode of Q3 reverse biased. In this way, only Q4 conducts
when the output is low
(ii) Explain in detail the generation of hamming code for 4- bit
data.(April 2019)
Step1:If the number of data bits is designated as d, then the number of parity
bit p can be found by the following relationship,
• 2p ≥ d + p +1
Here d=4 , let p=3
23 = 4+3+1=8
Step2 : Draw Bit position table
Let the four bit data be 0101

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Step: Check for parity.

For Even parity

P1 checks bits positions 1, 3, 5 and 7 = P1,0,1,1

To satisfy even parity P1=0
P2 checks bits positions 2,3, 6 and 7 = P2,0,0,1
To satisfy even parity P2 =1
P3 checks bits positions 4,5, 6 and 7 = P3, 1,0,1
To satisfy even parity P3 =0

Hamming code is 0101101

13. (i) Design a 2-input NOR gate using CMOS logic.

(ii) Explain the operation of RTL inverter circuit with relevant
diagrams. (April 2019)
(i) 2-input CMOS NOR gate.
P-channel MOSFET’s Q1 and Q2 are connected in series and n-
channel MOSFET’s Q3 and Q4 are connected in parallel. A LOW
at any input turns ON its corresponding p-channel MOSFET and
turns OFF its corresponding n-channel MOSFET, and vice versa for
a HIGH input
When A=B=0 , the PMOS Q1 ,Q2 are On and NMOS Q3 and Q4 are OFF.
Hence the output is high.
When A=0 and B=1 the PMOS Q1 is ON and Q2 is OFF and NMOS Q3
is OFF, Q4 is ON.Hence the output is Low

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When A=1 and B=0 the PMOS Q1 is OFF and Q2 is ON and NMOS Q3
is ON, Q4 is ON.Hence the output is OFF
When A=B=1 PMOS Q1 ,Q2 are OFF and NMOS Q3 and Q4 are ON.
Hence the output is low.

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(ii)RTL inverter
A bipolar transistor switch is the simplest RTL gate (inverter or NOT gate)
implementing logical negation. It consists of a common-emitter stage with
a base resistor connected between the base and the input voltage source.
The role of the base resistor is to expand the very small transistor input
voltage range (about 0.7 V) to the logical "1" level (about 3.5 V) by
converting the input voltage into current. Resistance is chosen low enough
to saturate the transistor and high enough to obtain high input resistance.
The role of the collector resistor is to convert the collector current into
voltage; its resistance is chosen high enough to saturate the transistor and
low enough to obtain low output resistance (high fan-out).

When A=0 ,the transistor is OFF ,hence output is high

When A=1, the transistor is ON and output becomes low
14. i) Find the decimal equivalent of the following binary numbers expressed
in the 2’s complement format 00001110; 10001110. (3)
(a) The MSB bit is ‘0’, which indicates a plus sign.
The magnitude bits are 0001110.
The decimal equivalent=
0x 2^{0}+ 1x 2^{1}+ 1x 2^{2}+ 1x 2^{3}+ 0x 2^{4}+ 0x 2^{5}+ 0x 2^{6}
=0+ 2+ 4+ 8+ 0+ 0+ 0=14

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Therefore, 00001110 represents +14

(b) The MSB bit is ‘1’, which indicates a minus sign
The magnitude bits are therefore given by the 2’s complement of 0001110,
i.e. 1110010
The decimal equivalent=
0x 2^{0}+ 1x 2^{1}+ 0x 2^{2}+ 0x 2^{3}+ 1x 2^{4}+ 1x 2^{5}+ 1x 2^{6}
=0+ 2+ 0+ 0+ 16+ 32+ 64=114
Therefore, 10001110 represent −114
ii) Explain in detail about cyclic redundancy check code for digital code
transmission and reception. (5)
A cyclic redundancy check (CRC) is an error-detecting code commonly
used in digital networks and storage devices to detect accidental changes to
raw data. Blocks of data entering these systems get a short check value
attached, based on the remainder of a polynomial division of their contents.
CRC or Cyclic Redundancy Check is a method of detecting accidental
changes/errors in the communication channel. CRC uses Generator
Polynomial which is available on both sender and receiver side.
iii) Explain in detail about Ex-NOR gate and draw the CMOS logic
diagram of it. (5) (Nov/ Dec 2020: May 2021)
Complementing the output of an XOR gate, gives XNOR gate.
The XNOR function in Boolean notation is

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15. i) Why is ECL called nonsaturating logic ? What is the main advantage
accruing from this ? With the help of a relevant circuit schematic, briefly
describe the operation of ECL OR/NOR logic. (6)
Emitter-coupled logic (ECL) is a BJT-based logic family which is generally
considered as the fastest logic available.It has the highest speed of any of the
currently-available logic circuits. It is primarily due to the fact that transistors
never operate fully saturated of cut-off. Hence Emitter Coupled Logic (ECL)
is known as non-saturated logic.
Advantage:
• High-speed operation is possible and so the fastest logic family.
• Since transistors are not allowed to enter into saturation, which
reduces the storage delay.
• Fan-out capability is high.

A B OUTPUT-1(NOR) OUTPUT-2(OR)
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1
• When A=B=0 the Q2,Q1 = off but Q3 will be ON
Hence Vout1 = 1 , Vout2=0
• If any one input A or B is 1 , then the corresponding transistor Q2 /Q1
conducts .Hence Vout 1 =0

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• When current through Q2,Q1 increases , then the current through the
reference transistor Q3 decreases making Q3 OFF.Therefore if any one
of the input A,B is high , then Q3 will be oFF
ii) With neat internal schematic diagram explain BiCMOS logic two
input NAND gate. (7) (Nov/ Dec 2020: May 2021)
The two input BICMOS NAND gate consists of
1) 2 PMOS PA and PB
2) 4 NMOS, NA1, NB1, NA3, NB3
3) Two BJT's QP and Q0
NAND GATE TRUTHTABLE
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Case 1 : Both VA and VB are low.

If both the inputs VA and VB are low(0). PA and PB will be ON and the base
of QA will be high. Thus the top BJT(QA) will be ON which pulls the output
UP . If there is a capacitive load. The output current will be almost 101 times
the base current i.e it will be 101IB (Assuming beta of transistor is 100). N2
MOS is getting input from the base of QA transistor. Since the base of QA is
HIGH (say 5v), it will on N2 MOS. Since N2 is ON, it will Pull the base
Charge out of Q0 transistor. So, if both the inputs are low, QA is ON and Q0
is OFF. Output is high and output current is large. For high switching speeds

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of the BJT's, we need to remove the base charge from the transistor. In order
to remove the charge from the base of the transistor 3 NMOS are used

Case 2 :When VA is low , PA is ON which supplies base of Qp and when VB

is high NB1 is ON hence Vout is high.
Case 3: When VA is high , PA is OFF which supplies base of Qp and when
VB is low PB is ON hence Vout is high

Case 4 : VA and VB are high

NB3 and NA3 NMOS make sure that QA is in OFF state. PA and PB are OFF.
NB1, NA1 will be ON. The output is discharged via NB1, NA1 and Q0. (High
Speed). N2 will be effectively out of circuit in this case. So, Q0 is ON and QP
is OFF.

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