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VLSI Interview Preparation Notes Final

The document provides comprehensive notes on VLSI interview preparation, covering key concepts such as MOSFET operation, characteristics, and sizing, as well as CMOS inverter design and power dissipation. It discusses various technical aspects including capacitances, noise margins, delay expressions, and power minimization techniques. Additionally, it highlights the importance of layout considerations and transistor-level design for efficient circuit performance.

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4 views3 pages

VLSI Interview Preparation Notes Final

The document provides comprehensive notes on VLSI interview preparation, covering key concepts such as MOSFET operation, characteristics, and sizing, as well as CMOS inverter design and power dissipation. It discusses various technical aspects including capacitances, noise margins, delay expressions, and power minimization techniques. Additionally, it highlights the importance of layout considerations and transistor-level design for efficient circuit performance.

Uploaded by

mail2meetbc
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI Interview Preparation Notes

1) Explain why & how a MOSFET works:

A MOSFET is a voltage-controlled device that regulates current flow between drain and source by applying

voltage to the gate terminal. The gate forms an electric field that either allows or blocks current depending on

whether Vgs exceeds threshold voltage (Vth). Operation modes include cutoff, triode, and saturation.

2) Vds-Ids Curve for a MOSFET:

- Linear region (Ohmic): Id proportional to Vds.

- Saturation region: Id becomes constant.

(a) Increasing Vgs: Id increases, curve shifts upward.

(b) Increasing width (W): Higher current, steeper curves.

(c) Channel Length Modulation: Saturation curve gets a slope, Id increases with Vds.

3) MOSFET Capacitances:

Cgs, Cgd, Csb, and Cdb are parasitic capacitances. They affect switching speed and power dissipation. Cgd

(Miller Capacitance) impacts delay significantly.

4) CMOS Inverter and Transfer Characteristics:

Consists of PMOS and NMOS. Transfer characteristic has regions - logic high, transition, and logic low.

Defines noise margins and switching threshold.

5) Sizing of Inverter:

PMOS has lower mobility, so it is sized larger (typically 2-3x NMOS) for equal rise/fall delay.

6) Sizing to Increase Threshold Voltage:

Decrease W/L ratio or apply body biasing (increase Vsb).

7) Noise Margin:

NMH = VOH - VIH; NML = VIL - VOL. Determined from inverter VTC curve intersections.

8) CMOS Switching Power Dissipation:

P = alpha C_L V^2 f


9) Body Effect:

Increase in Vth due to increase in source-bulk voltage (Vsb).

10) Effects of Scaling:

Faster switching, reduced area, higher leakage, short-channel effects.

11) CMOS Delay Expression:

Delay approximately R x C = V/I x C

12) Delay vs Load Capacitance:

Directly proportional; increased load increases delay.

13) Delay with Output Resistance:

Extra output resistance increases total RC delay.

14) Limitation of Increasing VDD:

Higher power, reliability issues, breakdown risk, more leakage.

15) Resistance of Metal Lines:

Increases with length, decreases with width/thickness.

16) Signal Interference in Metal Lines:

- Out-of-phase: Crosstalk noise on middle line.

- In-phase: Less interference.

17) Increasing Vias:

Reduces resistance and improves reliability.

18) Two-input NAND Gate Transistor Level Sizing:

(a) Vth tuning by sizing; (b) Equal rise/fall: wider PMOS.

19) Optimizing Delay for Late Signal:


Place late-arriving signal (A) closer to output (last NMOS).

20) NOR Gate Stick Diagram:

Series PMOS and parallel NMOS. Minimize diffusion breaks.

21) Power Minimization Techniques:

Clock gating, power gating, multi-Vth design, voltage scaling.

22) Charge Sharing:

Occurs when precharged nodes share charge. Can disturb logic levels.

23) Gradual Inverter Sizing in Buffers:

Reduces delay and input loading. Large inverter loads previous stage.

24) Parallel Small Transistors vs One Large:

Better matching, layout yield, easier manufacturing.

25) Layout to Circuit Extraction:

Identify diffusion, polysilicon, metal interconnects to draw circuit.

26) AOI Gate:

Logic: NOT(A.B + C); Draw transistor level & stick diagram.

27) Transmission Gate:

Using only NMOS or PMOS leads to degraded signal. Combine both to pass full swing logic.

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