1.

​ Explain why & how a MOSFET works: A MOSFET (Metal Oxide

Semiconductor Field Effect Transistor) works by controlling the flow of
current between the source and drain terminals using an electric field
generated by a voltage applied to the gate terminal. In an nMOS, when Vgs
> Vth (threshold voltage), an inversion layer (channel) forms, allowing
electrons to flow. In a pMOS, the channel forms when Vgs < Vth, allowing
hole conduction.
2.​ Draw Vds-Ids curve for a MOSFET and show how it changes with (a)
increasing Vgs (b) increasing transistor width (c) channel length modulation:
●​ The Vds-Ids curve has two regions: linear and saturation. (a) Increasing Vgs
increases the current in both regions. (b) Increasing transistor width
increases current proportionally. (c) Channel length modulation introduces a
non-zero slope in the saturation region, showing that Ids increases with Vds.
3.​ Explain the various MOSFET Capacitances & their significance: MOSFET
capacitances include Cgs (gate-source), Cgd (gate-drain), Csb (source-bulk),
and Cdb (drain-bulk). These capacitances influence switching speed,
dynamic power, and delay.
4.​ Draw a CMOS Inverter. Explain its transfer characteristics: A CMOS
inverter uses a PMOS (connected to Vdd) and NMOS (connected to GND).
The transfer curve shows three regions: output high, transition region, and
output low. The transition region defines the noise margins and inverter
threshold voltage.
5.​ Explain sizing of the inverter: PMOS is sized larger (typically 2-3 times)
than NMOS due to its lower mobility, to balance the rise and fall times.
6.​ How do you size NMOS and PMOS transistors to increase the threshold
voltage? Decrease W/L ratio or apply body bias to increase Vsb, which
increases Vth due to body effect.
7.​ What is Noise Margin? Explain the procedure to determine Noise Margin:
Noise margin defines the tolerance to noise without logic level flipping.
NMH = VOH - VIH, NML = VIL - VOL, determined from inverter transfer
characteristics.
8.​ Give the expression for CMOS switching power dissipation: P = alpha * CL
* Vdd^2 * f, where alpha is activity factor, CL is load capacitance, and f is
frequency.
9.​ What is Body Effect? Body effect is the increase in threshold voltage due to
a non-zero source-to-bulk voltage.
10.​Describe the various effects of scaling: Scaling reduces delay and area, but
increases leakage, power density, and short-channel effects.
11.​Give the expression for calculating Delay in CMOS circuit: Delay = RC =
(Vdd / Id) * CL, where R is effective resistance and CL is load capacitance.
12.​What happens to delay if you increase load capacitance? Delay increases
linearly with load capacitance.
13.​What happens to delay if we include a resistance at the output of a CMOS
circuit? Added resistance increases RC delay, hence increases overall delay.
14.​What are the limitations in increasing the power supply to reduce delay?
Higher Vdd increases power quadratically, risks breakdown and reliability
issues.
15.​How does Resistance of the metal lines vary with increasing thickness and
increasing length? Resistance increases with length and decreases with
thickness/width.
16.​You have three adjacent parallel metal lines. Two out-of-phase signals pass
through the outer lines. Draw the waveforms in the center line due to
interference. Now draw for in-phase signals: Out-of-phase: noise due to
capacitive coupling. In-phase: less noise due to signal cancellation.
17.​What happens if we increase the number of contacts or via from one metal
layer to the next? Reduces resistance and improves reliability.
18.​Draw a transistor level two input NAND gate. Explain its sizing: Two
PMOS in parallel and two NMOS in series. (a) Sizing affects Vth; (b) PMOS
sized 2x NMOS for balanced delays.
19.​Let A & B be two inputs of the NAND gate. Say A arrives later. Which
NMOS is placed near output? Place A near output to reduce delay.
20.​Draw the stick diagram of a NOR gate. Optimize it: Use minimum diffusion
breaks and shared diffusion regions to reduce area and delay.
21.​For CMOS logic, give techniques to minimize power consumption: Clock
gating, power gating, multiple threshold CMOS, dynamic voltage scaling,
reduce switching activity.
22.​What is Charge Sharing? Explain the problem while sampling data from a
Bus: Charge sharing occurs when precharged nodes share charge, leading to
voltage droop and incorrect logic levels.
23.​Why do we gradually increase the size of inverters in buffer design? To
avoid large capacitive load on preceding stage and reduce delay.
24.​In large inverter design, why prefer small transistors in parallel? Improves
layout density, matching, and reduces parasitics.
25.​Given a layout, draw its transistor level circuit: Identify NMOS and PMOS
connected using diffusion and poly layers, derive the logic gate structure.
26.​Give the logic expression for an AOI gate. Draw transistor level equivalent
and stick diagram: AOI21: Y = NOT((A AND B) OR C). PMOS:
parallel-series; NMOS: series-parallel. Stick diagram reflects layout.
27.​Why don't we use just one NMOS or PMOS as a transmission gate? NMOS
can't pass strong '1', PMOS can't pass strong '0'. Transmission gate uses both
for full swing logic.
28.​For a NMOS transistor acting as a pass transistor with gate at VDD, what is
output for input pulse from 0 to VDD? NMOS passes 0 well but passes
VDD only up to VDD-Vth, resulting in degraded high level.
29.​Draw a 6-T SRAM Cell and explain Read and Write operations: Consists of
two cross-coupled inverters and two access transistors. Write: word line
enabled, bit lines drive data. Read: word line enabled, bit lines sensed.
30.​Draw the Differential Sense Amplifier and explain its working: Compares
small voltage difference between bit and bit-bar. Uses positive feedback for
fast decision. Sizing depends on required speed and matching.
31.​What happens if we use an Inverter instead of Sense Amplifier? Inverter is
less sensitive; may fail to detect small voltage swings.
32.​Draw the SRAM Write Circuitry: Write drivers force data on bit lines during
write. Word line enables access.
33.​Approximate sizes of transistors in SRAM: Pulldown > Access > Pullup.
Typical ratio 3:2:1 based on stability and speed trade-off.
34.​How does size of PMOS pull-ups affect SRAM performance? Larger PMOS
improves restoring but makes writing harder.
35.​What is the critical path in SRAM? Read path through bitline and sense
amplifier.
36.​Draw the timing diagram for SRAM Read. What if clock is delayed?
Delayed clock delays sense amplifier enable, reducing performance or
failing read.
37.​Big picture of SRAM Layout: Array of cells in center, row/column decoders
on sides, sense/write circuits nearby, buffers at periphery.
38.​Preferred metal layers for Word and Bit lines: Bitlines: Metal1 (dense,
vertical); Wordlines: Metal2 (horizontal, cross routing).
39.​How to model SRAM at RTL Level: Use reg array and FSM for control;
emulate read/write/access protocols.
40.​What’s the difference between Testing & Verification? Verification ensures
logic correctness before fabrication. Testing checks for faults after
fabrication.
41.​For AND-OR MUX, how to test Stuck-At faults? Apply vectors to control
lines and observe outputs. Stuck-at-0: check if output is stuck low;
Stuck-at-1: output stuck high.
42.​What is Latch-Up? How to avoid it? Latch-up is a short circuit due to
parasitic thyristor between VDD and GND. Prevent by guard rings, well
spacing, and substrate contacts.