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DLD 03 Comb Logic Design Part1

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24 views22 pages

DLD 03 Comb Logic Design Part1

Uploaded by

Ishmam Bhuiyan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Logic and Computer Design Fundamentals

Chapter 3 – Combinational
Logic Design
Part 1 – Introduction and Encoder

Charles Kime & Thomas Kaminski


© 2004 Pearson Education, Inc.
Terms of Use
(Hyperlinks are active in View Show mode)
Overview
 Part1 - Introduction
 Design Topics
• Design hierarchy
 Design Procedure
• The major design steps: specification, formulation,
optimization, technology mapping, and verification
 Technology Mapping
• From AND, OR, and NOT to other gate types
• Decoders
 Part 2
• Encoders
• Multiplexers
• Binary Adders

Chapter 3 - Part 1 2
Combinational Circuits
 A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
 A block diagram:
Combinatorial
Logic
Circuit

m Boolean Inputs n Boolean Outputs


Chapter 3 - Part 1 3
Decoding
 Decoding - the conversion of an n-bit input
code to an m-bit output code with
n £ m £ 2n such that each valid code
word produces a unique output code
 Circuits that perform decoding are called
decoders
 Here, functional blocks for decoding are
• called n-to-m line decoders, where m £ 2n, and
• generate 2n (or fewer) minterms for the n input
variables
Chapter 4 4
Decoder Examples
 1-to-2-Line DecoderA D0 D1
D0 5 A
0 1 0
1 0 1 A D1 5 A
 2-to-4-Line Decoder (a) (b)
A0
A1 A0 D 0 D1 D2 D3
A1
0 0 1 0 0 0 D0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A 1 A 0

(a)
D2 5 A 1 A 0
 Note that the 2-4-line
made up of 2 1-to-2- D3 5 A 1 A 0
line decoders and 4 AND
(b)
gates. Chapter 4
Decoder with Enable
 In general, attach m-enabling circuits to the outputs
 See truth table below for function
• Note use of X’s to denote both 0 and 1
• Combination containing two X’s represent four binary combinations
 Alternatively, can be viewed as distributing value of signal
EN to 1 of 4 outputs EN
A
 In this case, called a 1

A
demultiplexer 0
D 0

EN A 1 A 0 D0 D1 D2 D3 D1

0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0

(b)
Chapter 4 6
2-to-4 Decoder Diagram

Chapter 3 - Part 1 7
NAND Only

D0 E. A1. A0

D1 E. A1. A0

D2 E. A1. A0

D0 E. A1. A0

Chapter 3 - Part 1 8
Decoder Expansion
 General procedure given in book for any decoder with
n inputs and 2n outputs.
 This procedure builds a decoder backward from the
outputs.
 The output AND gates are driven by two decoders with
their numbers of inputs either equal or differing by 1.
 These decoders are then designed using the same
procedure until 2-to-1-line decoders are reached.
 The procedure can be modified to apply to decoders
with the number of outputs ≠ 2n

Chapter 4 9
3-to-8-line decoder (without enable)
 Consider a 3-to-8-line decoder (without enabler)
A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1
0 0 1 1
0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1
1 1 0 1

1 1 1 1

Chapter 4 10
3-to-8-line Decoder Implementation

Chapter 3 - Part 1 11
Easier way by Expansion
 Decoder expansion
• Combine two or more small decoders with
enable inputs to form a larger decoder
 3-to-8-line decoder constructed from two 2-to-
4-line decoders
 The MSB is connected to the enable inputs
 if A2=0, upper is enabled; if A2=1, lower is
enabled.

Chapter 3 - Part 1 12
Expansion

Chapter 3 - Part 1 13
Combinational Circuit Design with Decoders

 Combinational circuit implementation with


decoders
• A decoder provide 2n minterms of n input
variables
• Since any Boolean function can be expressed
as a sum of minterms, one can use a decoder
and external OR gates to implement any
combinational function.

Chapter 3 - Part 1 14
Combinational Circuit Design with Decoders

 Realize F (X,Y,Z) = Σ (1, 4, 7) with a decoder:

Chapter 3 - Part 1 15
Decoder Implementation of a Full Adder

 Truth Table: We have two outputs, called S, which stands for


sum, and C, which stands for carry. Both sum and carry are
functions of X, Y, and Z.

Chapter 3 - Part 1 16
Decoder Implementation of a Full Adder

 The output functions S & C can be expressed in sum-of-minterms


forms as follows:

 S is implemented by taking minterms 1, 2, 4, and 7 and the OR


gates forms the logical sum of minterm for S
 Similarly, carry C is implemented by taking logical sum of
minterms 3, 5, 6, and 7 from the same decoder

Chapter 3 - Part 1 17
Spring 2024 Question 6
Spring 2024 Question 6
Fall 2023 Question 5
Fall 2023 Question 5
Thank You

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