Computer Architecture

and Organization
UNIT II
 SYLLABUS

 Instruction formats – Three Address Instructions, Two Address Instructions, One Address Instructions,
Zero Address Instructions, RISC Instructions,
 Addressing modes – Numerical Example,
 Data Transfer and manipulation – Data Transfer Instructions, Data Manipulation Instructions, Arithmetic
Instructions, Logical and Bit Manipulation Instructions, Shift Instructions,
 Program control – Status Bit Conditions, Conditional Branch Instructions, Subroutine Call and Return,
Program Interrupt, Types of Interrupts,

2
 INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the
effective address is determined
The number of address fields in the instruction format depends on the internal
organization of CPU

- The three most common CPU organizations:

Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
ADD
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THREE and TWO-ADDRESS INSTRUCTIONS

Three-Address Instructions:

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1 M[A] + M[B] */
ADD R2, C, D /* R2 M[C] + M[D] */
MUL X, R1, R2 /* M[X] R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1 M[A] */

ADD R1, B /* R1 R1 + M[B] */
MOV R2, C /* R2 M[C] */
ADD R2, D /* R2 R2 + M[D] */
MUL R1, /* R1 R1 * R2 */
R2 /* M[X] R1 */
MOV X, R1
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ONE and ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions:
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
Zero-Address Instructions:
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */

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RISC Instructions:
- Program to evaluate X = (A + B) * (C + D) :
 ADDRESSING MODES

Addressing Modes:

* Specifies a rule for interpreting or modifying the

address field of the instruction (before the operand
is actually referenced)

* Variety of addressing modes

- to give programming flexibility to the user

- to use the bits in the address field of the
instruction efficiently

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 TYPES OF ADDRESSING MODES
Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP],
EA: Effective Address.

Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

Register Mode
Address specified in the instruction is the register
address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory 14
 TYPES OF ADDRESSING MODES

Register Indirect Mode

Instruction specifies a register which contains
the memory address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)

Auto-increment or Auto-decrement features:

Same as the Register Indirect, but:
- When the address in the register is used
to access memory, the
value in the register is incremented or
decremented by 1 (after or before
the execution of the instruction)

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 TYPES OF ADDRESSING MODES
Direct Address Mode
Instruction specifies the memory address which
can be used directly to the physical memory
- Faster than the other memory addressing
modes
- Too many bits are needed to specify the
address for a large physical memory
space
- EA = IR(address), (IR(address): address field of
IR)

Indirect Addressing Mode

The address field of an instruction specifies the address of a
memory location that contains the address of the operand
- When the abbreviated address is used, large physical memory can
be
addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory
access
- EA = M[IR(address)] 16
 TYPES OF ADDRESSING MODES
Relative Addressing Modes
The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a
designated register to calculate the address of the operand

PC Relative Addressing Mode(R = PC)

- EA = PC + IR(address)
- Address field of the instruction is short
-Large physical memory can be accessed with a small number of
address bits

Indexed Addressing Mode

XR: Index Register:
- EA = XR +
IR(address)
Base Register Addressing
Mode
BAR: Base Address
Register:
- EA = BAR + 17
IR(address)
ADDRESSING MODES - EXAMPLES
Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction

R1 = 400

399 450
XR = 100 700
400

AC
500 800

900
600
Addressing Effective Content
Mode Address of AC
Direct address 500 /* AC  (500) */ 800 325
702
Immediate operand - /* AC  500 */ 500
Indirect address 800 /* AC  ((500)) */ 300
Relative address 702 /* AC  (PC+500) */ 325 300
Indexed address 600 /* AC  (XR+500) */ 900 800
Register - /* AC  R1 */ 400
Register indirect 400 /* AC  (R1) */ 700
Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450

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 DATA TRANSFER INSTRUCTIONS
Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

Data Transfer Instructions with Different Addressing Modes

Assembly
Mode Convention Register Transfer
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC  M[M[ADR]]
Relative address LD $ADR AC  M[PC + ADR]
Immediate operand LD #NBR AC  NBR
Index addressing LD ADR(X) AC  M[ADR + XR]
Register LD R1 AC  R1
Register indirect LD (R1) AC  M[R1]
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1]
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DATA MANIPULATION INSTRUCTIONS
Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions

Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI
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PROGRAM CONTROL INSTRUCTIONS
+1
In-Line Sequencing
(Next instruction is fetched from the
PC next adjacent location in the memory)

Address from other source; Current Instruction, Stack, etc

Branch, Conditional Branch, Subroutine, etc

Program Control Instructions

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN * CMP and TST instructions do not retain their
Compare(by - ) CMP results of operations(- and AND, respectively).
Test (by AND) TST They only set or clear certain Flags.

Status Flag Circuit A B

8 8
c7
8-bit ALU
c8
F7 - F0
V Z S C
F7
Check for 8
zero output
F 21
CONDITIONAL BRANCH INSTRUCTIONS

Mnemonic Branch condition Tested condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Unsigned compare conditions (A - B)
BHI Branch if higher A
> B BHE Branch if higher or equal A
 B BLO Branch if lower A
< B BLOE Branch if lower or equal A
 B BE Branch if equal A
=B
BNE Branch if not equal A
B

Signed compare conditions (A - B)

BGT Branch if greater than A
> B BGE Branch if greater or equal A
 B BLT Branch if less than A
<B
BLE Branch if less or equal A
B
BE Branch if equal A
=B 22
BNE Branch if not equal A
 SUBROUTINE CALL AND RETURN
SUBROUTINE CALL Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save
return address
Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine

- Same as the Branch or Conditional Branch

* Save the Return Address to get the address

of the location in the Calling Program upon
exit from the Subroutine CALL
- Locations for storing Return Address: SP  SP - 1
• Fixed Location in the M[SP]  PC
PC  EA
subroutine(Memory)
• Fixed Location in memory RTN
• In a processor Register PC  M[SP]
• In a memory stack SP  SP + 1
- most efficient way
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 PROGRAM INTERRUPT
Types of Interrupts:
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure

Internal interrupts (traps)

Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation

Software Interrupts
Both External and Internal Interrupts are initiated by the computer Hardware.
Software Interrupts are initiated by executing an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations
which are not allowed in the user mode

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 INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or
an external signal rather than from the execution
of an instruction (except for the software
interrupt)

- The address of the interrupt service program is

determined by the hardware rather than from
the address field of an instruction

- An interrupt procedure usually stores all the

information necessary to define the state of CPU
rather than storing only the PC.

The state of the CPU is determined

from; Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state depending on 25