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#5 Slide Set 11

The document outlines an assignment on error detection using parity bits, including their application, differences between even and odd parity, and the necessary components for generating even parity bits. It also discusses sequential logic circuits, differentiating between asynchronous and synchronous circuits, and describes various types of storage elements like latches and flip-flops. Additionally, it provides details on specific flip-flop types such as RS, JK, D, and T flip-flops, along with their characteristics and applications.

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4 views26 pages

#5 Slide Set 11

The document outlines an assignment on error detection using parity bits, including their application, differences between even and odd parity, and the necessary components for generating even parity bits. It also discusses sequential logic circuits, differentiating between asynchronous and synchronous circuits, and describes various types of storage elements like latches and flip-flops. Additionally, it provides details on specific flip-flop types such as RS, JK, D, and T flip-flops, along with their characteristics and applications.

Uploaded by

turgutkhansabo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 26

Digital Logic

Design
Lecture Set 11

Dr. Usman Ali Shah

Department of Computer Science


Islamia College University, Peshawar, Pakistan
Fall 2024
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Assignment 2
• Explain how parity bits are used for error detection.
• Can we use them for error correction?
• What is the difference between even parity and odd parity?
• What is the number of error-bits that can be detected using parity
bits?
• Which gate is used to generate even parity bits?
• Draw a truth table and schematic for generating an even parity bit for
a FOUR-bit (4-bit) message.

• Note:
• Maximum six handwritten pages
• Clearly write your name and roll number on the first page
• Must be stapled properly before submission
• Viva will be conducted to mark the assignment
3 of 26

Assignment 2
• Submission and viva
• BSCS 3A: Monday, 30th December 2024
• BSCS 3B: Thursday, 2nd January 2025
• BSSE 3A: Thursday, 2nd January 2025
• BSSE 3B: Tuesday, 31st December 2024
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Assignment 2 – Helping Slide


• Use of a parity bit is the simplest error detection method
• An extra bit is added to the original data item to make
• the total number of 1’s even – called even parity
• the total number of 1’s odd – called odd parity
• After transmission, the receiver can detect the presence
of errors by counting the number of 1’s
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Assignment 2 – Helping Slide


• Textbook - Digital Design with Verilog by Morris Mano 5°
Edition
• Pages: 26-27
• Pages: 106-108
SEQUENTIAL LOGIC
Circuits WITH feedback
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Sequential Circuits
• Can store the results of previous inputs
• Output depends on
• Present inputs and
• The state of the storage elements
• Have feedback
• Have memory elements
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Sequential Circuits
• A time sequence of
• Inputs
• Outputs
• Internal states
9 of 26

Sequential Circuits
• Two Types based on Timing:
1. Asynchronous Circuits:
• No separate clock signal
• Behavior of depends upon the input signals at any instant of time
and the order in which the inputs change
• Instability problem makes their design difficult

2. Synchronous Circuits:
• Generally, use a separate clock signal
• Behavior can be defined from the knowledge of its signals at
discrete instants of time, based on clock pulses
• Simpler to design
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Clocked Synchronous Circuits


• Clock signal has a periodic train of clock pulses.
• The clock pulses are distributed throughout the system
• storage elements are affected only with the arrival of each pulse
• Clock pulses determine when computational activity will
occur within the circuit
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Clocked Synchronous Circuits


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Temporary Storage Elements


• Binary storage devices capable of storing one bit of
information
• As long as power is supplied
• Two types
• Latches
• Flip-Flops
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Latches
• Level-Triggered: Latches change their output state
based on the level of their input signals
• Asynchronous: Latches don't require a clock signal
• Sensitive to Input Changes: Latches are constantly
monitoring their inputs and will update their output
whenever there is a change.
• Less Robust: More chances of errors
14 of 26

Flip-Flops
• Flip-flops use latches as their building blocks
• Use clock signals
• Edge-Triggered: Change output state based on the edge
of a clock signal.
• Synchronous: Need a clock signal to synchronize their
operation
• Less Sensitive to Input Changes: Flip-flops only sample
their inputs at the specific clock edge
• More Robust: Less chance of errors
15 of 26

RS Latch
• Aka SR Latch
• Direct-coupled / Unclocked RS flip-flop
• A circuit with
• two cross-coupled NOR gates or
• two cross-coupled NAND
• Two inputs labeled
• S for set and
• R for reset.
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RS Latch

• Problem: Undefined / meta-stable state when S=R=1


17 of 26

RS Latch with NAND – Just for info

• Aka R’S’ Latch


• Problem: Undefined / meta-stable state when S=R=0
18 of 26

RS Flip-Flop
• Clocked RS Latch
• Consists of
• A simple RS Latch
• With two additional AND gates
• For combining S and R with clock signal
• Works when the clock signal is high
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RS Flip-Flop

• Problem: Undefined for S=R=1


20 of 26

JK Flip Flop
• A refined form of RS flip-flop
• J = Set
• K = Reset (Clear)
• Klear
• When J = K = 1
• Inverts the output
• Thus, solving the problem of undefined state
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JK Flip Flop
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D Flip Flop
• Single-input version of RS flip-flop
• Has a single input called D
• For data
• D goes to S
• Complement of D goes to R
• An extra inverter needed
• Usually built using NAND gates
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D Flip Flop
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T Flip Flop
• A single-input version of the JK flip-flop
• Toggles the output when the input T = 1
• Obtained if J and K inputs of a simple JK flip-flop are tied
together
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T Flip Flop
26 of 26

Just for info


• You will learn in Computer Architecture that
• Cache memory is built from flip-flops
• Mostly D flip-flops
• Very fast
• Expensive
• RAM is built from capacitors
• Less speed than cache memory
• Reduces cost

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