•Inverter : basic requirement for

producing a complete range of

Logic circuits

1 0 Vo

0 1

Vss

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 Vdd
Basic Inverter: Transistor with source
connected to ground and a load resistor
connected from the drain to the positive
Pull-Up Supply rail
R

Vo Output is taken from the drain and control

input connected between gate and ground

Resistors are not easily formed in silicon

Vin - they occupy too much area
Pull Down

Transistors can be used as the pull-up device

Vss

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 NMOS Depletion Mode Transistor Pull - Up
Vdd
• Pull-Up is always on – Vgs = 0; depletion
D
• Pull-Down turns on when Vin > Vt

• With no current drawn from outputs, Ids

for both transistors is equal
Vo S

V0 Vt
Vdd D
Vin

S
Non-zero output
Vss

Vi
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 Ids
Vgs=0.2VDD
Ids
Vgs=0

Vgs=-0.2 VDD

Vgs=-0.4 VDD

Vgs=-0.6VDD
Vds VDD –Vds
Vin

Vgs=VDD
VDD
Ids Vgs=0.8VDD

Vgs=0.6 VDD

Vgs=0.4 VDD
Vgs=0.2VDD

Vds Vo
VDD VDD

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 Decreasing
Vin Zpu/Zpd

VDD
Increasing
Zpu/Zpd

Vo
VDD
Vinv

• Point where Vo = Vin is called Vinv

• Transfer Characteristics and Vinv can be shifted by altering ratio

of pull-up to Pull down impedances

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 Cascading NMOS Inverters

When cascading logic devices care must be taken

to preserve integrity of logic levels

i.e. design circuit so that Vin = Vout = Vinv

Determine pull – up to pull-down ratio for driven inverter

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 Assume equal margins around inverter; Vinv = 0.5 Vdd
Assume both transistors in saturation, therefore: Ids = K (W/L) (Vgs – Vt)2/2

Depletion mode transistor has gate connected to source, i.e. Vgs = 0

Ids = K (Wpu/Lpu) (-Vtd)2/2

Enhancement mode device Vgs = Vinv, therefore
Ids = K (Wpd/Lpd) (Vinv – Vt)2/2
Assume currents are equal through both
channels (no current drawn by load)

(Wpd/Lpd) (Vinv – Vt)2 = (Wpu/Lpu) (-Vtd)2

Convention Z = L/W

Vinv = Vt – Vtd / (Zpu/Zpd)1/2

Substitute in typical values Vt = 0.2 Vdd ;
Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd
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This gives Zpu / Zpd = 4:1 for an nmos
 Pull-Up to Pull-Down Ratio for an nMOS inverter driven
through 1 or more pass transistors

Inverter 1 Vdd Vdd Inverter 2

A B C

Vin1 Vout2

It is often the case that two inverters are connected via a series of switches (Pass Transistors)
We are concerned that connection of transistors in series will degrade the logic levels into
Inverter 2. The driven inverter can be designed to deal with this. (Zpu/Zpd >= 8/1)

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 Complimentary Transistor Pull – Up (CMOS)

Vdd

Vout Vtn Vtp

P on N on
Vin Vo
N off P off
Both On

Vin
Vss Vdd
Vss
Logic 0 Logic 1
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Vout Vtn Vtp

1: Logic 0 : p on ; n off
P on N on
N off P 5: Logic 1: p off ; n on

Both On off
2: Vin > Vtn.
Vdsn large – n in saturation
Vdsp small – p in resistive
Small current from Vdd to Vss
Vin
4: same as 2 except reversed p and n
Vss Vdd
3: Both transistors are in saturation
Large instantaneous current flows
1 2 3 4 5

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 CMOS Inverter VOUT vs. VIN
VOUT

both curve very steep

sat. here; only in
VDD
“C” for small
interval of VIN
NMOS:
cutoff
NMOS: NMOS:
PMOS:
triode triode
triode
PMOS: PMOS:
NMOS: cutoff
saturation
saturation
PMOS:
triode
VIN
6/3/2015 A B C D E
VDD 202
CMOS INVERTER CHARACTERISTICS

Current through n-channel pull-down transistor n

n VDD  Vtp  Vtn
In Vin  V tn 2 Vin 
 2 
 1 p n
Current through p-channel pull-up transistor  p

p
If n = p and Vtp = –Vtn

I p  2  Vin VDD   
At logicVthreshold,
tp In = Ip 2 Vin  VDD
2

n p
2 in
V 
Vtn
2

2
 Vin  VDD  Vtp 
 pW p W
 n n
 
 2 Lp Ln
n
Vin  Vtn 
2  2
p
 Vin  V DD   tpV
Mobilities are unequal : µn = 2.5 µp
n 
   Vin  VDD  Vtp
 p Vin  Vtn Z = L/W

  n  n
Vin 1   Vtn  VDD  Vtp
  p  p Zpu /Z = 2.5:1 for a symmetrical CMOS inverter
pd
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 Beta Ratio(β)
• If βp / βn  1, switching point will move from
VDD/2
VDD
p
 10
n
2
Vout
1
0.5
p
 0.1
n

0
VDD
Vin
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 BICMOS inverter
• As in NMOS and CMOS logic circuitry, the
basic logic element is the inverter circuit.
• When designing with BICMOS in mind, the
logical approach is to use
1.MOS switches to perform the logic function
and
2.transistors to drive the output loads.
• A simple BICMOS inverter as shown in figure
• It consists of two bipolar transistors T1 and
T2 with one NMOS transistor T3, and one
PMOS transistor T4.
• If Vin =0 Volts T3=OFF so T1 will be non-
conducting T4 = ON so supplies current to
base of T2 which will conduct and act as a
current source to charge the load CL
towards +5 Volts.
• If Vin =+5 Volts T4=OFF so T2 will be non-
conducting T3= ON so supplies current to
base of T1 which will conduct and act as
current sink to the load CL discharge it
towards ‘0’.
• CL will be charged or discharged rapidly.
• The output logic levels will be good.
• The inverter has a high input impedance.
• The inverter has a low output impedance.
• The inverter has a high current drive capability
• The inverter has high noise margins.
 DRAWBACK
• There is a DC path between VDD and GND
through T3 and T1. Due to these there will
significant static current flow when Vin = Logic 1.
• When Vin = VDD , T4- OFF and no conducting path
to the base of T2
• When Vin= 0, T3-OFF and no conducting path to
the base of T1 So it will slow down the action of
the circuit.
 An improved version of BICMOS
•An improved version of this circuit is given in which the DC path
through T3 and T1 is now eliminated, but the output voltage swing
now reduced
 An improved version of BICMOS
• An improved version arrangement is
taken by using resistors, is shown in
Figure .
1. The circuit resistors provide
the improved swing of
output voltage when each
bipolar transistor is off, and
also provide discharge
paths for base current
during turn-off.
2. Due to presence of the
resistor in the circuit it is
inconvenient because it take
more amount of area.
 An improved version of
BiCMOS:-
In this circuit, the transistors
T5 and T6 are arranged to turn
on when T2 and T1respectively
are being turned off.
In general, BiCMOS inverters offer
many advantages where high load
current sinking and sourcing is
required. The arrangements lead on
to the BiCMOS gate circuits
 LATCH UP INCMOS
Latch-up is a condition in which the parasitic components
give rise to the establishment of low-resistance conducting
paths between VDD and VSS with disastrous results. Careful
control during fabrication is necessary to avoid this
problem.
One benefit of the BiCMOS process is that it produces circuits
which are less to suffer from latch-up problems.
This is due to several factors:
1.A reduction of substrate resistance Rs.
2. A reduction of n-well resistance Rw.
LATCH UP