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Tejo B. Shankar Pothuraju: Education

Tejo B. Shankar Pothuraju is pursuing a Master of Science in Electrical Engineering from the University of Maryland College Park. He received a Bachelor of Technology in Electronics and Electrical Engineering from Indian Institute of Technology Guwahati, India. His skills include programming languages like C, C++, Verilog, System Verilog, Python and Java. He has work experience in validation of wireless systems at Qualcomm and design verification at Mirafra Software Technologies. He also has research experience applying machine learning techniques for fraud detection. His academic projects involve thermal-aware floorplanning, image compression and virtual memory simulation.

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78 views

Tejo B. Shankar Pothuraju: Education

Tejo B. Shankar Pothuraju is pursuing a Master of Science in Electrical Engineering from the University of Maryland College Park. He received a Bachelor of Technology in Electronics and Electrical Engineering from Indian Institute of Technology Guwahati, India. His skills include programming languages like C, C++, Verilog, System Verilog, Python and Java. He has work experience in validation of wireless systems at Qualcomm and design verification at Mirafra Software Technologies. He also has research experience applying machine learning techniques for fraud detection. His academic projects involve thermal-aware floorplanning, image compression and virtual memory simulation.

Uploaded by

Shankar Pothuraju
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Tejo B.

Shankar Pothuraju

9314 Cherry Hill Road, Apt 307, College Park, MD 20740


(301)676-7512, pothuraju.shankar@gmail.com, www.linkedin.com/in/shankarpothuraju

EDUCATION

Master of Science in Electrical Engineering


University of Maryland College Park
Bachelor of Technology in Electronics and Electrical Engineering
Indian Institute of Technology Guwahati, India

SKILLS

Languages and Tools


Protocols

ACADEMIC
PROJECTS

Implementation of thermal-aware floorplanner using simulated annealing


Spring 2016
o Implemented a floorplanner which is optimized both in area and max temperature at steady state of blocks,
where dimensions and avg. power of blocks are given.
o Integrated Hotspot with floorplanner to obtain steady state temperatures of blocks for a given configuration.
o Applied simulated annealing algorithm to find optimal floorplan which is represented using sequence pair.
Implementation of optimal 4-bit Multiplier
Spring 2016
o Implemented 4-bit multiplier which is optimal in speed and dynamic power.
o Employed optimization techniques at architecture and circuit level such as logic reduction, transistor sizing.
Image Compression using Embedded Zero Tree and adaptive DCT Quantization table
Spring 2016
o Implemented Embedded Zero Tree algorithm, part of JPEG 2000 standard.
o Implemented EZT to transform DWT coefficients to dominant and subordinate coefficients and back.
o Formulated DCT quantization table based on variance and dynamic range of luminance and chrominance.
o Achieved better compression with lower losses compared to JPEG 1992 standard.
Virtual Memory Simulator
Fall 2015
o Implemented Intel i7 memory hierarchy system with three level caches, virtual physical memory and 3 levels of
TLBs using Python.
o Simulated complete flow of memory transactions involved in load, store operations.

WORK
EXPERIENCE

May 2017(Expected)
GPA : 3.733 out of 4
June 2013
GPA : 8.02 out of 10

C, C++, Verilog, System Verilog, Python, Java, Assembly, R, MATLAB, Virtuoso


USB 2.0, SPI

Development of algorithms for Power Quality Monitoring using Machine Learning


Aug 2012 -April 2013
o Independently studied suitability of signal processing techniques such as DWT, adaptive filtering for de-noising,
detection and time localization of power quality disturbances.
o Implemented DWT, adaptive filtering to de-noise and extract features of power-quality waveforms.
o Applied support vector machines and probabilistic neural networks to classify power-quality waveforms (both
one-on-one and one-on-all classifications of power quality disturbances).
Campus wide Distributed Public Addressing System via Ethernet
Jan 2012-April 2012
o Developed Ethernet transmitter and receiver for audio signals by programming Ethernet controllers, Arduino
Uno development boards, DAC, ADC.
Qualcomm India Pvt. Ltd.
Bangalore, India
Engineer I, Post-Si Validation
Feb 2015 June 2015
o Involved in validation of FM and Bluetooth cores of wireless subsystem of three Qualcomm MSMs.
o Modified test cases to suit specifications of MSMs and employed equipment automation for FM tests using
Python.
Mirafra Software Technologies Pvt. Ltd.
Bangalore, India
Engineer I, Design Verification
Feb 2014 June 2015
o Involved in all the stages of ASIC design verification.
o Contributed in identifying features and conceiving test plans to optimally verify USB 2.0 core, Memory
Controller and SPI controller.
o Implemented test plan independently using System Verilog to verify Memory Controller and SPI Master Core.
o Applied constraint random verification to verify Memory Controller design.
Infosys Limited
Bangalore, India
Junior Research Associate
July 2013 Jan 2014
o Developed Proof of Concept model to identify frauds in financial companies (in the order of millions) using
Machine learning.
o Implemented multivariate outlier techniques such as Mahalanobis distance algorithm using R programming
software and Java.

Digital Computer Design, Digital CMOS VLSI Design, Embedded Systems, Image and Video Processing, Algorithms.
RELEVANT
COURSEWORK

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