CK COLLEGE OF ENGINEERING AND TECHNOLOGY

ELECTRONICS AND COMMUNICATION ENGINEERING

EC6016 – OPTO ELECTRONIC DEVICE
COURSE DATA SHEET
PROGRAM: UG DEGREE: B.E
COURSE: VLSI DESIGN SEMESTER: VI CREDITS: 3
COURSE CODE: EC8095
COURSE TYPE: CORE
REGULATION: 2017
COURSE AREA/DOMAIN: ECE CONTACT HOURS: 5 hours/ Week
CORRESPONDING LAB COURSE CODE LAB COURSE NAME (IF ANY):- VLSI
(IF ANY): EC8661 DESIGN LABORATORY
SYLLABUS:
UNIT DETAILS HOURS
INTRODUCTION TO MOS TRANSISTOR
MOS Transistor, CMOS logic, Inverter, Pass Transistor, Transmission gate,
Layout Design Rules, Gate Layouts, Stick Diagrams, Long-Channel I-V
I 9
Characteristics, C-V Characteristics, Non ideal I-V Effects, DC Transfer
characteristics, RC Delay Model, Elmore Delay, Linear Delay Model,
Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling.
COMBINATIONAL MOS LOGIC CIRCUITS
Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch
II Logic, Dynamic Circuits, Pass Transistor Logic, Transmission Gates, 9
Domino, Dual Rail Domino, CPL, DCVSPG, DPL, Circuit Pitfalls. Power:
Dynamic Power, Static Power, Low Power Architecture.

SEQUENTIAL CIRCUIT DESIGN

Static latches and Registers, Dynamic latches and Registers, Pulse
III Registers, Sense Amplifier Based Register, Pipelining, Schmitt Trigger, 9
Monostable Sequential Circuits, Astable Sequential Circuits. Timing
Issues : Timing Classification Of Digital System, Synchronous Design.

DESIGN OF ARITHMETIC BUILDING BLOCKS AND

SUBSYSTEM
Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters,
IV ALUs, power and speed tradeoffs, Case Study: Design as a tradeoff. 9
Designing Memory and Array structures: Memory Architectures and
Building Blocks, Memory Core, Memory Peripheral Circuitry.

V IMPLEMENTATION STRATEGIES AND TESTING 9

FPGA Building Block Architectures, FPGA Interconnect Routing
Procedures. Design for Testability: Ad Hoc Testing, Scan Design, BIST,
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IDDQ Testing, Design for Manufacturability, Boundary Scan.

TOTAL HOURS 45

TEXT / REFERENCE BOOKS:

Text
BOOK TITLE / AUTHORS / PUBLICATION
/ Ref.
Neil H.E. Weste, David Money Harris ―CMOS VLSI Design: A Circuits and Systems
T1
Perspective‖, 4th Edition, Pearson , 2017 (UNIT I,II,V)
Jan M. Rabaey ,Anantha Chandrakasan, Borivoje. Nikolic, ‖Digital Integrated Circuits:A
T2
Design perspective‖, Second Edition , Pearson , 2016.(UNIT III,IV)

R1 M.J. Smith, ―Application Specific Integrated Circuits‖, Addisson Wesley, 1997

Sung-Mo kang, Yusuf leblebici, Chulwoo Kim ―CMOS Digital Integrated Circuits:Analysis &
R2
Design‖,4th edition McGraw Hill Education,2013

R3 Wayne Wolf, ―Modern VLSI Design: System On Chip‖, Pearson Education, 2007

R.Jacob Baker, Harry W.LI., David E.Boyee, ―CMOS Circuit Design, Layout and Simulation‖,
R4
Prentice Hall of India 2005.

COURSE PRE-REQUISITES:
COURSE
COURSE NAME DESCRIPTION SEM
. CODE
EC8252 Electronic Devices  To gain knowledge on working of transistors II

COURSE OBJECTIVES:
S. No COURSE OBJECTIVE
1 To Study the fundamentals of CMOS circuits and its characteristics.

2 Understanding and realization of combinational digital circuits.

3 Understanding and realization of sequential digital circuits.

4 Impart Knowledge on Architectural choices and performance tradeoffs involved in

designing and realizing the circuits in CMOS technology
5 Understanding the different FPGA architectures and testability of VLSI circuits.

Form No.AC 25 Rev.No.00 Effective Date: 22-02-2018

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COURSE OUTCOMES: At the end of course the students shall able to

PO(1..12) & PSO(1..2)
S. No DESCRIPTION Blooms
MAPPING
To Realize the concepts of digital building PO1, PO2, PO3, PO4, PO5, PO6,
EC8095.1 blocks using MOS transistor. L2
PO11 PO12, PS01, PSO2
EC8095.2 To Design combinational MOS circuits PO1, PO2, PO3, PO4, PO5, PO12,
and power strategies. L4
PS01, PSO2
EC8095.3 To Design and construct Sequential PO1, PO2, PO3, PO4, PO5, PO12,
Circuits and Timing systems. L2
PS01, PSO2
EC8095.4 To Design arithmetic building blocks and PO1, PO2, PO3, PO4, PO6, PO11
memory subsystems. L3
PO12, PS01, PSO2
EC8095.5 Apply and implement FPGA design flow PO1, PO2, PO3, PO5, PO6, PO11
and testing. L2
PO12, PS01, PSO2
COURSE OUTCOMES VS POS MAPPING (DETAILED; HIGH:3; MEDIUM:2; LOW:1):
S. No DESCRIPTION PO PO PO PO PO PO PO PO PO PO PO PO PS PS
1 2 3 4 5 6 7 8 9 10 11 12 O1 O2
To Realize the
EC8095.1 concepts of digital 3 3 3 3 1 1 - - - - 1 2 3 2
building blocks using
MOS transistor.
To Design
EC8095.2 combinational MOS 3 2 3 2 1 - - - - - - 2 3 2
circuits and power
strategies.
To Design and
EC8095.3 construct Sequential 3 2 3 2 1 - - - - - - 2 3 2
Circuits and Timing
systems.
To Design arithmetic
EC8095.4 2 1 2 2 1 2 - - - - 1 2 3 3
building blocks and
memory subsystems.
Apply and implement
EC8095.5 3 - 2 - 2 2 - - - - 1 2 2 3
FPGA design flow
and testing.
EC8095 - 2.80 1.60 2.60 1.80 1.20 1.00 - - - - 0.60 2.00 2.80 2.40

* For Entire Course, PO /PSO Mapping; 1 (Low); 2(Medium); 3(High) Contribution to PO/PSO

Form No.AC 25 Rev.No.00 Effective Date: 22-02-2018

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PROGRAM OUTCOMES (PO) & PSO

Environment & Practical & Skill
PO1 Engineering Knowledge PO7 PSO1
Sustainability Development
Employment,
PO2 Problem Analysis PO8 Ethics PSO2 Entrepreneurship, Higher
Studies and Research
PO3 Design & Development PO9 Individual & Team Work
PO4 Investigations PO10 Communication Skills
PO5 Modern Tools PO11 Project Mgt. & Finance
PO6 Engineer Society PO12 Life Long Learning

JUSTIFICATION FOR MAPPING

S. No. PO / PSO MAPPED JUSTIFICATION
PO1: In-depth knowledge of engineering is required to
understand the basics of electron device
PO2: Review on various logic problems
PO3: Design various logic gates
PO1, PO2, PO3, PO4, PO4: Data based on research analysis
EC8095.1 PO5, PO6, PO11 PO12, PO5: Tools for studying logic design
PS01, PSO2 PO6: Develop best suited logic circuits for society
PO11: Project on various logic gate functionality
PO12: Constant updation with the recent trends is provided
PSO1: Practical experimentation in logic circuits
PSO2: Ability to do research in transitor
PO1: A good engineering fundamental is required to define the
combinational circuits
PO2: Formulate problems on power consumption
PO3: Design solutions for combinational circuits
EC8095.2 PO1, PO2, PO3, PO4, PO4: Use Research based knowledge for performance analysis
PO5, PO12, PS01, PSO2
PO5: Tools for designing circuits
PO12: Constant updation with the recent trends is provided
PSO1: Practical Testing for circuits power consumption
PSO2: Ability to do research in power reduction techniques
PO1: A good engineering fundamental is required to define the
sequential circuits
PO2: Formulate problems on timing issues
PO3: Design solutions for sequential circuits
EC8095.3 PO1, PO2, PO3, PO4, PO4: Use Research based knowledge for performance analysis
PO5, PO12, PS01, PSO2
PO5: Tools for designing sequential circuits circuits
PO12: Constant updation with the recent trends is provided
PSO1: Practical Testing for timing issues in circuits
PSO2: Ability to do research in clock signalling

Form No.AC 25 Rev.No.00 Effective Date: 22-02-2018

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PO1: Adequate ability to illustrate the various arithmetic

building blocks is acquired through applying the necessary
engineering concepts
PO2: Formulate problems on Booths Algorithm
PO3: To cater the societal needs in Arithmetic function
PO1, PO2, PO3, PO4, PO5
EC8095.4 PO6, PO11 PO12, PS01, PO4: Data based on research analysis
PO5: Tools for designing efficient models
PSO2
PO6: Develop efficient arithmetic blocks for engineer society
PO11: Management skill in project on adders
PO12: Updates through constant learning
PSO1: Experimenting the various arithmetic building blocks
PSO2: Research in characteristics of adders, multipliers
PO1: Competent analytical and engineering knowledge is needed
to know about the architecture of FPGA
PO3: The societal needs are to be met with a keen eye on
environmental considerations for developing integrated circuits
PO5: Tool essential for designing Integrated Circuits
EC8095.5 PO1, PO3, PO5, PO6, PO6: Serve society doing customized FPGA boards
PO11 PO12, PS01, PSO2 PO11: Project management on developing FPGA boards
PO12: Interested on the developing standards and a thirst to stay
updated with the latest trends
PSO1: IC designing skill is developed
PSO2: Ability to do research in FPGA to apply design principles
for developing quality products

GAPS IN THE SYLLABUS - TO MEET INDUSTRY/ PROFESSION REQUIREMENTS, POs: (it can
also address)
S.
DESCRIPTION PROPOSED ACTIONS
No
1 Fabrication of Transistors

2 FAULTS IN DIGITAL TESTING SYSTEMS

TOPICS BEYOND SYLLABUS / ADVANCED TOPICS / DESIGN:

1 EFFICIENT METHODOLOGY FOR ACHIEVING OPTIMAL POWER AND SPEED IN ASIC

PROPOSED ACTIONS: ASSIGNMENT / INDUSTRY VISIT / GUEST LECTURES / NPTEL ETC

WEB SOURCE REFERENCES:
1 http://www.infocobuild.com/education/audio-video-courses/electronics/AdvancedVLSIDesign-IIT-Bombay/
lecture-09.html

Form No.AC 25 Rev.No.00 Effective Date: 22-02-2018

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2 https://www.youtube.com/watch?v=_oJKuzGFdgQ

DELIVERY / INSTRUCTIONAL METHODOLOGIES:

☐ CHALK & TALK ☐STUD. ☐WEB RESOURCES ☐ NPTEL/OTHERS
ASSIGNMENT
☐ LCD/SMART ☐ STUD. ☐ ADD-ON COURSES ☐ WEBINARS
BOARDS SEMINARS

ASSESSMENT METHODOLOGIES – DIRECT

☐ASSIGNMENTS ☐ STUD. SEMINARS ☐ TESTS / MODEL ☐UNIV.
EXAMS EXAMINATION
☐ STUD. LAB ☐ STUD. VIVA ☐ MINI / MAJOR ☐ CERTIFICATIONS
PRACTICES PROJECTS
☐ ADD-ON ☐ OTHERS
COURSES

ASSESSMENT METHODOLOGIES – INDIRECT

☐ ASSESSMENT OF COURSE OUTCOMES (BY ☐ STUDENT FEEDBACK ON FACULTY
FEEDBACK (ONCE) (TWICE)
☐ ASSESSMENT OF MINI / MAJOR PROJECTS ☐ OTHERS
BY EXT. EXPERTS

INNOVATIONS IN TEACHING / LEARNING / EVALUATION PROCESSES:

1. Power Point Presentation
2. Animated Video

Faculty In-charge HoD PRINCIPAL

Form No.AC 25 Rev.No.00 Effective Date: 22-02-2018