Scribd
Upload
52 views1 page

Verilog HDL Assignment 1

This document is a question bank for the subject Verilog HDL for the 5th semester Electronics and Communication Engineering students at the Cambridge Institute of Technology. It contains 10 questions related to Verilog HDL and digital design methodology. The questions cover topics like the definition of HDLs, the emergence of HDL languages, digital design flow, module definition in Verilog, and writing Verilog code for gate-level designs like a 4-bit ripple carry counter. The question bank was prepared by the assistant professor Girish H.

Uploaded by

Mr girish
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
52 views1 page

Verilog HDL Assignment 1

This document is a question bank for the subject Verilog HDL for the 5th semester Electronics and Communication Engineering students at the Cambridge Institute of Technology. It contains 10 questions related to Verilog HDL and digital design methodology. The questions cover topics like the definition of HDLs, the emergence of HDL languages, digital design flow, module definition in Verilog, and writing Verilog code for gate-level designs like a 4-bit ripple carry counter. The question bank was prepared by the assistant professor Girish H.

Uploaded by

Mr girish
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

CAMBRIDGE INSTITUTE OF TECHNOLOGY

Department of Electronics and Communication Engineering


K.R.Puram, Bengaluru-560036

Subject: Verilog HDL Semester: V


Subject code: 18EC56 Section: A & B

Question Bank

SL. QUESTIONS CO RBT


NO
Level

1. What is HDL? What are the two types of HDL Languages CO1 L1
2. Explain the Emergence of Hardware Description Language CO1 L1

3 Explain the typical Digital Design Flow CO1 L2


4. a. A 4-bit ripple carry adder (Ripple_Add) contains four 1-bit full adders (FA). CO1 L1
i. Define the module FA.
ii. Define the module Ripple_Add

5. Write about popularity of Verilog HDL CO1 L2

6. Explain Trends in HDL CO1 L2

7. Define module and module instance with an example CO1 L2

8. Write Verilog code( Design block) for Negative edge triggered 4 bit ripple CO1 L2
carry counter in gate level description
9. Explain with neat block diagram top down design methodology and bottom CO1 L2
up design methodology
10. Write Verilog stimulus code for Negative edge triggered 4 bit ripple carry CO1 L2
counter in gate level description

Prepared by

Girish H

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy