Lab4 Djm30073-Ring Counters
Lab4 Djm30073-Ring Counters
DJM30073-DIGITAL SYSTEM
SESSION : ..............
PRACTICAL TASK 4 [CLO2P, PLO5]
LEARNING OUTCOMES:
Students should be able to:-
1. Understand the operation of left shifted and right shifted ring counters.
2. Analyze the output sequences of left shifted and right shifted ring counters.
3. Distinguish the characteristics of left shifted and right shifted ring counters.
4. Apply an application of shift register as ring counters.
EQUIPMENT REQUIRED:
1. 74LS174 Quad D flip-flop with reset and clear.
2. Light emitting diode (LED).
3. Resistors (100Ω).
4. Push button switch
5. DC Power Supply 5V.
6. Digital Multimeter.
7. Breadboard.
8. Jumper wires.
THEORY:
Shift registers consist of an arrangement of flip-flops for temporary storage and transfer data in digital system.
There are four types of shift registers which is SISO (serial in serial out), SIPO (serial in parallel out), PISO (parallel in
serial out) and PIPO (parallel in parallel out). One of the applications of shift register in digital system is shift register
counter. A shift register counter is basically a shift register with the serial output connected back to the serial input to
produce special sequences. These devices are often classified as counters because they exhibit a specified sequence of
states. One of them is a ring counter.
The ring counter utilizes one flip-flop for each state in its sequence. It has the advantage that decoding gates are
not required for decimal conversion, because there is an output for each decimal number.
The following circuit as in Figure 1.1 is a 4-bit ring counter constructed from D flip-flops. The output of each
stage is shifted into the next stage on the positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops
except the first one FF0 are reset to 0. FF0 is preset to 1 instead.
CLOCK Q0 Q1 Q2 Q3
3
4
CLOCK Q0 Q1 Q2 Q3
4
5
7
8
3. Explain the way to connect preset and clear of each flip-flop for 4-bit right shifted ring counter for producing the
following output at initial state of ring counter. (Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 0)
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4. Explain the way to connect preset and clear of each flip-flop for 4-bit right shifted ring counter for producing the
following output at initial state of ring counter. (Q0 = 0, Q1 = 1, Q2 = 1, Q3 = 0)
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DISCUSSION:
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CONCLUSION:
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