Flip flops

Sequential Digital Circuits

• Sequential circuits are digital circuits in which the outputs
depend not only on the current inputs, but also on the
previous state of the output.
• They basic sequential circuit elements can be divided in two
categories:
• Level-sensitive (Latches)
– High-level sensitive
– Low-level sensitive
• Edge-triggered (Flip-flops)
– Rising (positive) edge triggered
– Falling (negative) edge triggered
– Dual-edge triggered
Flip flop
• A basic sequential circuit is a flip-flop
• Flip-flop has two stable states of
complementary output values
4 Basic types of Flip-Flops
• SR Flip Flop
• JK Flip Flop
• D Flip Flop
• T Flip Flop
4 Basic types of Flip-Flops
• SR ff has 2 inputs, S (set) and R (reset)
that set or reset the output Q when
asserted
• JK ff has 2 inputs, J and K need to be
asserted at the same time to change the
state
• D ff has 1 input D (DATA), which sets the
ff when D = 1 and resets it when D = 0
• T ff has1 input T (Toggle), which forces
the ff to change states when T = 1
SR Flip flop
• SR (set-reset) flip-flop can be represented
as two nor gates or two nand gates
Circuit Diagram Truth Table
R
Q S R Q+ Q΄+ Function

0 0 Q Q΄ Latch
0 1 0 1 Reset
1 0 1 0 Set
Q
S 1 1 0 0 Illegal

S
Q Logic Symbol

S Q

R Q
Q
R
SR Flip flop
• This type of flip-flop has two inputs: Set
and Reset.
• Two outputs: Q and Q' (Q' being the
inverse of Q).
• The SR flip-flop can also have a clock
input for a level driven circuit as opposed
to a pulse driven circuit
SR Flip flop
• The operation of an SR flip-flop is as
follows: The Set input will make Q goto 1
i.e. will 'set' the output.
• The Reset input will make the output Q
goto 0 i.e. reset the output.
• The scenerio of having both Set and Reset
at logic 1 is not allowed as this is not a
logical pair of inputs.
SR Flip flop
SR Flip flop
Present State Next State Inputs Map entry
S R
0 0 0 X r
0 1 1 0 S
1 0 0 1 R
1 1 X 0 s

State Change Diagram

Exercise
• For a given S and R inputs to SR flip-flop,
sketch the output signal Q
Exercise

Q
Answer
The Gated Set/Reset (SR) Latch
• To be able to control when the S and R
inputs of the SR latch can be applied to the
latch and thus change the outputs, an extra
input is used.
• This input is called the Enable.
• If the Enable is 0 then the S and R inputs
have no effect on the outputs of the SR latch.
• If the Enable is 1 then the Gated SR latch
behaves as a normal SR latch.
The Gated Set/Reset (SR) Latch

Circuit Diagram Truth Table Truth Table

S EN S R Q+ EN S R Q+ Function
S Q Q
0 0 0 Q 0 X X
EN

R Q Q 0 0 1 Q 1 0 0
R
0 1 0 Q 1 0 1
0 1 1 Q 1 1 0
Logic Symbol
1 0 0 Q 1 1 1

S Q 1 0 1 0
EN 1 1 0 1
R Q
1 1 1 U
Exercise

(a) (b)

Set Enable

Reset Set

Reset
Q

Q
D type flip-flop (Delay)
• The D type flip-flop has one data input 'D'
and a clock input. The circuit edge triggers
on.the clock input. The flip-flop also has
two outputs Q and Q' (where Q' is the
reverse of Q).
D type flip-flop (Delay)

Circuit Diagram Truth Table Truth Table

D EN D Q Q+ EN D Q+ Function
S Q Q
0 0 0 Q 0 0
EN
0 0 1 Q 0 1
R Q Q
0 1 0 Q 1 0
0 1 1 Q 1 1
Logic Symbol
1 0 0 0
D Q
1 0 1 0
EN
1 1 0 1
Q
1 1 1 1
D type flip-flop (Delay)

INPUT CIRCUIT ACTION PRESENT NEXT INPUT MAP

D Q(TIME t+1) STATE STATE D ENTRY

0 0 0 0 0 0

1 1 0 1 1 D or 1
1 0 0 0
1 1 1 D or 1
JK flip-flop
• The JK type flip-flop consists of two data
inputs: J and K, and one clock input.
There are again two outputs Q and Q'
(where Q' is the reverse of Q).
JK flip-flop

INPUT CIRCUIT ACTION

J K Q(TIME t+1)
0 0 Q(t)

0 1 0

1 0 1

1 1 Q(t)’
JK flip-flop
PRESENT NEXT INPUT MAP ENTRY
STATE STATE
J K J K

0 0 0 X 0 X

0 1 1 X 1 X

1 0 X 1 X 1

1 1 X 0 X 0
The JK Latch
• Another way to ensure that the S and R inputs can
not be at logic 1 simultaneously, is to cross
connect the Q and Q’ outputs with the S and R
inputs through AND gates.
• The latch obtained is called the JK latch. In the J
and K inputs are both 1 then the Q output will
change state (Toggle) for as long as the Enable 1,
thus the output will be unstable.
• This problem is avoided by ensuring that the
Enable is at logic 1 only for a very short time,
using edge detection circuits.
The JK Latch

Circuit Diagram Truth Table Truth Table

EN J K Q Q+ EN J K Q+ Function
J S Q Q
0 X X X Q 0 X X
EN
1 0 0 0 0 1 0 0
K R Q Q
1 0 0 1 1 1 0 1
1 0 1 0 0 1 1 0
Logic Symbol
1 0 1 1 0 1 1 1
J Q 1
1 1 0 0
EN
1 1 0 1 1
K Q
1 1 1 0 1
1 1 1 1 0
Exercise
Complete the timing diagrams for :
(a)D Latch
(b)JK Latch
Assume that for both cases the Q output is
initially at logic zero.
Exercise

(a) (b)

Enable Enable

Data (D) J

K
Q

Q
T flip-flop (Triggered / Toggle)
• The T type flip-flop is a single input
device: T (trigger). Two outputs: Q and Q'
(where Q' is the inverse of Q).
T flip-flop (Triggered / Toggle)

INPUT CIRCUIT ACTION PRESENT NEXT INPUT MAP

T Q(TIME t+1) STATE STATE T ENTRY

0 Q(t) 0 0 0 0

1 Q(t)’ 0 1 1 T or 1
1 0 1 T or 1
1 1 0 0
Latches and Flip-Flops
• Latches are also called transparent or
level triggered flip flops, because the
change on the outputs will follow the
changes of the inputs as long as the
Enable input is set.
Latches and Flip-Flops
• Edge triggered flip flops are the flip
flops that change there outputs only at
the transition of the Enable input. The
enable is called the Clock input.
Edge Detection Circuits
• Edge detection circuits are used to detect
the transition of the Enable from logic 0 to
logic 1 (positive edge) or from logic 1 to
logic 0 (negative edge).
Edge Detection Circuits
• The operation of the edge detection
circuits shown on the next slide is based
on the fact that there is a time delay
between the change of the input of a gate
and the change at the output. This delay
is in the order of a few nanoseconds. The
Enable in this case is called the Clock
(CLK)
Edge Detection Circuits

Positive Edge Detection Negative Edge Detection

EN
EN' EN
EN'
EN
EN
EN

EN EN

EN

EN
EN

EN' EN'
The JK Edge Triggered Flip Flop
• The JK edge triggered flip flop can be
obtained by inserting an edge detection
circuit at the Enable (CLK) input of a JK
latch. This ensures that the outputs of the
flip flop will change only when the CLK
changes (0 to 1 for +ve edge or 1 to 0 for
–ve edge)
The JK Edge Triggered Flip Flop

Positive Edge JK Flip Flop Negative Edge JK Flip Flop

J J
S Q Q S Q Q

CLK CLK

R Q Q R Q Q
K K

CLK J K QN+1 Function CLK J K QN+1 Function

Logic Symbol Logic Symbol
X X Q X X
J Q J Q
0 0 Q 0 0
CLK CLK
K Q 0 1 0 K Q 0 1
1 0 1 1 0
1 1 Q’ 1 1
Example Timing

NO NO
SET TOGGLE TOGGLE CLEAR CHANGE SET CHANGE

CLK
JK Edge Triggered Flip Flop :- Example
Complete the timing diagrams for :
(a)Positive Edge Triggered JK Flip Flop
(b)Negative Edge Triggered JK Flip Flop
Assume that for both cases the Q output is
initially at logic zero.
JK Edge Triggered Flip Flop :- Example

(a) (b)

CLK CLK

J J

K K

Q Q
The D Edge Triggered Flip Flop
• The D edge triggered flip flop can be
obtained by connecting the J with the K
inputs of a JK flip through an inverter as
shown below. The D edge trigger can also
be obtained by connecting the S with the
R inputs of a SR edge triggered flip flop
through an inverter.
The D Edge Triggered Flip Flop

Positive Edge D Flip Flop Negative Edge D Flip Flop

D J Q Q D J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK D QN+1 Function Logic Symbol CLK D QN+1 Function
D Q X Q D Q X Q
CLK 0 CLK 0
0 0
Q Q 1
1 1 1
Example Timing

Q=D=1 Q=D=0 Q=D=0 Q=D=1 Q=D=1 Q=D=0 Q=D=0

No Change No Change No Change

CLK
The Toggle (T) Edge Triggered Flip
Flop
• The T edge triggered flip flop can be
obtained by connecting the J with the K
inputs of a JK flip directly. When T is zero
then both J and K are zero and the Q
output does not change. When T is one
then both J and K are one and the Q
output will change to the opposite state,
or toggle.
The Toggle (T) Edge Triggered Flip
Flop

Positive Edge T Flip Flop Negative Edge T Flip Flop

T J Q Q T J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK T QN+1 Function Logic Symbol CLK T QN+1 Function
T Q X Q T Q X Q
CLK 0 Q CLK 0 Q
Q 1 Q΄ Q 1 Q΄
D and T Edge Triggered Flip Flops :-
Example
Complete the timing diagrams for :
(a)Positive Edge Triggered D Flip Flop
(b)Positive Edge Triggered T Flip Flop
(c)Negative Edge Triggered T Flip Flop
(d)Negative Edge Triggered D Flip Flop
D and T Edge Triggered Flip Flops :-
Example
(a) (b)

CLK CLK

D D

Q Q

(c) (d)

CLK CLK

T T

Q Q
Flip Flops with asynchronous inputs
(Preset and Clear)
• Two extra inputs are often found on flip
flops, that either clear or preset the
output. These inputs are effective at any
time, thus are called asynchronous.
Flip Flops with asynchronous inputs
(Preset and Clear)
• If the Clear is at logic 0 then the output is
forced to 0, irrespective of the other
normal inputs. If the Preset is at logic 0
then the output is forced to 1, irrespective
of the other normal inputs.
Flip Flops with asynchronous inputs
(Preset and Clear)
• The preset and the clear inputs can not be
0 simultaneously. In the Preset and Clear
are both 1 then the flip flop behaves
according to its normal truth table.
Flip Flops with asynchronous inputs
(Preset and Clear)

Positive Edge JK Flip Flop with Preset and Clear

CLK PR CLR J K QN+1 Function

PRESET
PR
0 0 X X
J Q
0 1 X X 1
1 0 X X 0
K Q 1 1 0 0 Q
CLR
1 1 0 1 0
CLEAR
1 1 1 0 1
1 1 1 1 Q’
D Flip-Flop: PR & CLR Timing
Q=D=1 Q=D=0 Q=D=0 Q=D=1 Q=D=1 Q=D=0
Clocked Clocked Clocked Clocked Clocked Clocked

Q
Q=1 Q=1
Preset Preset

PR Q=0
Clear

CLR

CLK
JK Flip Flop With Preset and Clear:-
Example
Complete the timing diagrams for :
(a)Positive Edge Triggered JK Flip Flop
(b)Negative Edge Triggered JK Flip Flop.
Assume that for both cases the Q output is
initially at logic zero.
JK Flip Flop With Preset and Clear:-
Example

(a) (b)

CLK CLK

J J

K K

CLR CLR

PR PR

Q Q
• http://www.wisc-
online.com/objects/ViewObject.aspx?ID=DIG3303
• http://hyperphysics.phy-
astr.gsu.edu/hbase/electronic/jkflipflop.html
• http://computer.howstuffworks.com/boolean5.htm
• http://www.youtube.com/watch?v=bN02shtPWuI