VLSI Design and Testing 21EC63

Module 1
Introduction
The first integrated circuit was flip-flop with two transistors built by Jack Kilby at Texas
Instruments in the year 1958. In the year 2008, Intel’s Itanium microprocessor contained more
than 2 billion transistors and a 16 Gb Flash memory contained more than 4 billion transistors. So
in the range of over 50 years there is the growth rate is around 53%. This incredible growth has
come from steady miniaturization of transistors and improvements in manufacturing processes. As
transistors became smaller, they also became faster, dissipate less power, and are got cheaper to
manufacture. The memory once needed for an entire company’s accounting system is now carried
by a teenager in her iPod. Improvements in integrated circuits have enabled space exploration,
made automobiles safer and more fuel efficient, revolutionized the nature of warfare, brought much
of mankind’s knowledge to our Web browsers, and made the world a flatter place.
• During the first half of the twentieth century, electronic circuits used large, expensive,
power-hungry, and unreliable vacuum tubes.
• In 1947, John Bardeen and Walter Brattain built the first functioning point contact
transistor at Bell Laboratories, shown in Figure 1.1(a).
• Later it was introduced by the Bell Lab and named it as Transistor, T-R-A-N-S-I-S-T-O-
R, because it is a resistor or semiconductor device which can amplify electrical signals as
they are transferred through it from input to output terminals.
• Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization
if multiple transistors could be built on one piece of silicon. Figure 1.1(b) shows his first
prototype of an integrated circuit, constructed from a germanium slice and gold wires.

Fig. 1.1(a) First transistor (b) First Integrated Circuit

• Transistors are electrically controlled switches with a control terminal and two other
terminals that are connected or disconnected depending on the voltage or current applied
to the control.
• After the invention of point contact transistor, Bell Labs developed the bipolar junction
transistor, which were more reliable, less noisy and more power-efficient.
• Early integrated circuits used mainly bipolar transistors, which required a small current
into the control (base) terminal to switch much larger currents between the other two
(emitter and collector) terminals.
• The problem seen with bipolar transistors were the power dissipated by the base current
which limited the maximum number of transistors that can be integrated onto a single die.

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• Then in 1960 came Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The
advantages seen in MOSFETs were that they draw almost zero control current while idle.
It was available in 2 forms as: nMOS and pMOS, using n-type and p-type silicon,
respectively.
• In 1963, the first logic gates using MOSFETs was introduced at Fairchild. It included gates
used both nMOS and pMOS transistors. This gave the name Complementary Metal Oxide
Semiconductor, or CMOS. The circuits used discrete transistors but consumed only
nanowatts of power, which was about six times lesser than bipolar transistors.
• MOS ICs became popular because of their low cost, each transistor occupied less area and
the fabrication process was simpler. Early commercial processes used only pMOS
transistors but it suffered from poor performance, yield, and reliability. Later on Processes
using nMOS transistors became common in the 1970s.
• Even though nMOS process was less expensive compared to CMOS, nMOS logic gates
consumed power while they were idle. Power consumption became a major issue in the
1980s as hundreds of thousands of transistors were integrated onto a single die. CMOS
processes were widely adopted and have essentially replaced nMOS and bipolar processes
for nearly all digital logic applications.
• In 1965, Gordon Moore observed that plotting the number of transistors that can be most
economically manufactured on a chip gives a straight line on a semi-logarithmic scale.
Also he found transistor count doubling every 18 months. This observation has been called
Moore’s Law.
o Fig 1.2 shows that the number of transistors in Intel microprocessors has doubled
every 26 months since the invention of the 4004.
o Moore’s Law is based on scaling down the size of transistors and to some extent
building larger chips.

Fig 1.2 Transistors in Intel microprocessors

Level of Integration:
The process of integration can be classified as small, medium, large, very large.
1. Small-Scale Integration (SSI): The number of components is less than 10 in every package.
Logic Gates like inverters, AND gate, OR gate and etc. are products of SSI.

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2. Medium Scale Integration (MSI): MSI devices has a complexity of 10 to 100 electronic
components in a single package. Ex: decoders, adders, counters, multiplexers, and
demultiplexers.

3. Large Scale Integration (LSI): Products of LSI contain between 100 and 10,000 electronic
components in a single package. Ex: memory modules, I/O controllers, and 4-bit
microprocessor systems.

4. Very Large Scale Integration (VLSI): Devices that are results of VLSI contain between
10,000 and 300,000 electronic components. Ex: 8bit, 16-bit, and 32-bit microprocessor
systems.

• The feature size of a CMOS manufacturing process refers to the minimum dimension of a
transistor that can be reliably built. The 4004 had a feature size of 10μ m in 1971. The Core
2 Duo had a feature size of 45nm in 2008. Feature sizes specified in microns (10−6m),
while smaller feature sizes are expressed in nanometers (10−9 m).

MOS Transistor:
• Silicon (Si), a semiconductor, forms the basic starting material for most integrated
circuits
• Silicon is a Group IV element in periodic table, it forms covalent bonds with four
adjacent atoms, as shown in Figure 1.3(a). As the valence electrons of it are involved
in chemical bonds, pure silicon is a poor conductor.
• However its conductivity can be increased by introducing small amounts of impurities,
called dopants, into the silicon lattice.
• A dopant from Group V of the periodic table, such as arsenic, having five valence
electrons. It replaces a silicon atom in the lattice and still bonds to four neighbors, so
the fifth valence electron is loosely bound to the arsenic atom, as shown in Figure
1.3(b). Thermal vibration at room temperature is sufficient to free the electron. This
results in As+ ion and a free electron. The free electron can carry current and this is an
n-type semiconductor.

Fig 1.3 Silicon lattice and dopant atoms

• A Group III dopant, such as boron, having three valence electrons, as shown in Fig 1.3(c).
The dopant atom can borrow an electron from a neighboring silicon atom, which in turn
becomes short by one electron. That atom in turn can borrow an electron, and so forth, so
the missing electron, or hole, can propagate about the lattice. The hole acts as a positive
carrier so we call this a p-type semiconductor.
• A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers
of conducting and insulating materials to form a sandwich-like structure.

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• Transistors can be built on a single crystal of silicon, which are available as thin flat circular
wafer of 15–30 cm in diameter. CMOS technology provides two types of transistors an n-
type transistor (nMOS) and a p-type transistor (pMOS).
• Transistor operation is controlled by electric fields so the devices are also called Metal
Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. Cross-sections
and symbols of these transistors are shown in Figure 1.4. The n+ and p+ regions indicate
heavily doped n- or p-type silicon.

Fig 1.4 (a) nMOS transistor and (b) pMOS transistor

• Each transistor has conducting gate, an insulating layer of silicon dioxide (SiO2, also
known as glass), and the silicon wafer, also called the substrate/body/bulk. Gates of early
transistors were built from metal, so was called Metal-Oxide-Semiconductor, or MOS.
• Even though the gate has been formed from polycrystalline silicon (polysilicon), the name
is still metal.
• An nMOS transistor is built with a p-type body and has regions of n-type semiconductor
adjacent to the gate called the source and drain. They are physically equivalent and they
can be interchangeable. The body is typically grounded.
• A pMOS transistor is just the opposite, consisting of p-type source and drain regions with
an n-type body.
• In both the gate is the control input.
• nMOS Transistor:
o It controls the flow of electrical current between the source and drain.
o Considering an nMOS transistor, its body is generally grounded so the p–n
junctions of the source and drain to body are reverse-biased. If the gate is also
grounded, no current flows through the reverse-biased junctions and the transistor
is OFF.
o If the gate voltage is raised, it creates an electric field that starts to attract free
electrons to the underside of the Si–SiO2 interface.
o If the voltage is raised enough, the electrons outnumber the holes and a thin region
under the gate called the channel is inverted to act as an n-type semiconductor.
o Hence, a conducting path is formed from source to drain and current can flow. This
is the condition for transistor is ON state.
o Thus when the gate of an nMOS transistor is high, the transistor is ON and there is
a conducting path from source to drain. When the gate is low, the nMOS transistor
is OFF and almost zero current flows from source to drain.

• pMOS Transistor:
o The condition is reversed.
o The body is held at a positive voltage and also when the gate is at a positive voltage,
the source and drain junctions are reverse-biased and no current flows, the transistor is
OFF.

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o When the gate voltage is reduced, positive charges are attracted to the underside of the
Si–SiO2 interface. A sufficiently low gate voltage inverts the channel and a conducting
path of positive carriers is formed from source to drain, so the transistor is ON.
o The symbol for the pMOS transistor has a bubble on the gate, indicating that the
transistor behavior is the opposite of the nMOS.
o A pMOS transistor is just the opposite of that of nMOS. It is ON when the gate is low
and OFF when the gate is high
Transistor symbols and switch-level models is shown in Fig 1.5

Fig 1.5 Transistor symbols and switch-level models

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Multiplexers:
⚫ A multiplexer chooses the output from among several inputs based on a select signal.
⚫ A 2-input, or 2:1 multiplexer,
◆ Chooses input D0 when the select is 0
◆ Chooses input D1 when the select is 1.
⚫ The logic function is

⚫ Two transmission gates can be tied together to form a compact 2-input multiplexer.
⚫ The select and its complement enable exactly one of the two transmission gates at any given time.
⚫ The transmission gates produce a nonrestoring multiplexer.

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⚫ Build a restoring, inverting multiplexer out of gates.

⚫ Using Compound gates.
⚫ Using, gang together two tristate inverters.

Symbol
4:1 MUX:
⚫ Larger multiplexers can be built from multiple 2-input multiplexers.

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Sequential Circuits:
⚫ Combinational circuits, whose outputs depend only on the current inputs.
⚫ Sequential circuits have memory: their outputs depend on both current and previous inputs.
⚫ latches and flip-flops receive a clock, CLK, and a data input, D, and produce an output, Q.
⚫ A D-latch is transparent when CLK = 1, meaning that Q follows D.
⚫ It becomes opaque when CLK = 0, meaning Q retains its previous value and ignores changes
in D.
⚫ An edge-triggered flip-flop copies D to Q on the rising edge of CLK and remembers its old value
at other times.
Latches : D Latch:
⚫ A D-latch built from a 2-input multiplexer and two inverters.

⚫ The multiplexer can be built from a pair of transmission gates.

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⚫ When CLK = 1, the latch is transparent and D flows through to Q.

⚫ When CLK = 0, the latch becomes opaque, and a feedback path around the inverter pair is
established to hold the current state of Q indefinitely.

⚫ The D latch is also known as a level-sensitive latch

⚫ The state of the output is dependent on the level of the clock signal

Flop- Flop : Edge Triggered D-FF:

⚫ Edge-triggered flip-flop.
◼ Combining two level-sensitive latches
- one negative-sensitive and one positive-sensitive
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◼ The first latch stage is called the master and the second is called the slave.

⚫ While CLK is LOW, the master negative-level-sensitive latch output (QM) follows the D input
⚫ The slave positive-level-sensitive latch holds the previous value

⚫ When the CLK transitions from 0 to 1, the master latch becomes opaque and holds the D value at
the time of the clock transition.

⚫ The slave latch becomes transparent, passing the stored master value (QM) to the output of the
slave latch (Q).

⚫ The D input is blocked from affecting the output because the master is disconnected from the D
input

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⚫ This flip-flop copies D to Q on the rising edge of the clock.

⚫ Thus, this device is called a positive-edge triggered flip-flop.
⚫ Also called a
◆ D flip-flop
◆ D register
◆ Master–Slave flip-flop.

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Fig a. Capacitance effect at the gate terminal Fig b. Transistor dimensions

⚫ Drain to source current (Ids) depends on various parameter:

◆ Distance b/w drain and source (L)
◆ Channel width (w)
◆ Threshold Voltage(Vt)
◆ Thickness of oxide (tox)
◆ Mobility of carrier (μ)
◆ Oxide Permittivity (εox=3.9εo)

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⚫ The plot of current and voltage i.e., I-V Characteristics is shown in the fig.
pMOS Transistor:
pMOS transistors behave in the same way, but with the signs of all voltages and currents
reversed. The I-V characteristics are in the third quadrant, as shown in Fig.

Fig. Plot of I-V characteristics of (a) nMOS and (b) pMOS

Non ideal I-V Effects:

⚫ In Long- Channel IV Characteristics of the MOSFET, the equation for Current and Voltage
relationship was derived assuming certain number of Ideal Conditions.

Assumption: There will be no Current flow when the transistor is in off state.

⚫ But, practically there are lot of non- ideal effects which has to be considered by the designers to
model each design in more depth.

⚫ The device is said to be a short channel device if the length of the channel is of the same order of
magnitude as the depletion region thickness.

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Figure 2.14: Simulated and ideal I-V characteristics

⚫ In order to improve the performance and reduce the cost of production, one would prefer to scale
down the transistor size.

⚫ The effect of scaling is that it eliminates the stray capacitances that are present in overall device
which ultimately increases the speed of operation.

⚫ When the channel length is scaled down to the order of depletion region, a certain number of
non- ideal effects comes into picture.

⚫ The non-ideal IV Effects or Short Channel Effects for MOSFET are,

◼ Channel Length Modulation
◼ Mobility Degradation(Surface Scattering)
◼ Velocity Saturation
◼ Body Effect(Back Gate Effect)
◼ Leakage Current Effects
◆ Sub- threshold Conduction
◆ Gate Tunneling
◆ Reverse Bias Diode Current(Junction leakage)

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Mobility Degradation:

⚫ Practically, the electrons travel from source to drain in an nMOS do not follow a straight path.

⚫ A high voltage at the gate of the transistor attracts the carriers to the edge of the channel, causing
collisions with the oxide interface (carriers scattering off the silicon lattice) that slows the
carriers.This is called mobility degradation.

Velocity saturation:

⚫ At high field strength the carrier velocity ceases to increase linearly with the increase in field
strength.This is called velocity saturation.

⚫ Figure 2.15 shows measured data for carrier velocity as a function of the electric field, E,
between the drain and source. At low fields, the velocity increases linearly with the field.

⚫ The slope is the mobility, Reff. At fields above a critical level, Ec, the velocity levels out

at vsat, which is approximately 107 cm/s for electrons and 8 × 106 cm/s for holes

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⚫ As shown in the figure, the velocity can be approximated reasonably well with the following
expression

⚫ The new carrier velocity expression in EQ (2.24) gives modified equations for linear and
saturation currents

⚫ Note that μeff is a decreasing function of Vgs because of mobility degradation.

⚫ At sufficiently high lateral fields, the current saturates at some value dependent on the
maximum carrier velocity. Equating the two parts of EQ (2.26) at Vds = Vdsat lets us solve
for the saturation voltage

⚫ Noting that EQ (2.27) is in the same form as a parallel resistor equation, we see that Vdsat
is less than the smaller of VGT and Vc. Finally, substituting EQ (2.27) into EQ (2.26) gives
a simplified expression for saturation current accounting for velocity saturations:

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⚫ If VGT << Vc, velocity saturation effects are negligible and EQ (2.28) reduces to the square
law model. This is also called the long-channel regime. But if VGT >> Vc , EQ (2.28)
approaches the velocity-saturated limit

⚫ The α-power law model given in EQ (2.30) provides a simple approximation to capture this

behavior.

⚫ α is called the velocity saturation index and is determined by curve fitting measured I-V data.

⚫ Transistors with long channels or low VDD display quadratic I-V characteristics in saturation

and are modeled with α = 2.

⚫ As transistors become more velocity saturated, increasing Vgs has less effect on current and α
decreases, reaching 1 for transistors that are completely velocity saturated.
⚫ For simplicity, the model uses a straight line in the linear region. Overall, the model is based on

three parameters that can be determined empirically from a curve fit of I-V characteristics: α, G

Pc , and Pv.

⚫ Figure 2.16 compares the F-power law model against simulated results, using α= 1.3. The fit is
poor at low Vds, but the current at Vds = VDD matches simulation fairly well across the full
range of Vgs.

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⚫ Figure 2.17 plots Ids vs. Vgs (holding Vds = Vgs). This is equivalent to plotting Ion vs. VDD. For
Vgs significantly above Vt, Ids fits a straight line quite well. Thus, we can approximate the ON
current as

Channel length Modulation:

• Ideally drain current Ids is independent on Vds in the saturation region making transistor a
perfect current source.
⚫ The p–n junction between the drain and body forms a depletion region with a width Ld that
increases with Vdb, as shown in Figure 2.18.

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⚫ The depletion region effectively shortens the channel length to

⚫ To avoid introducing the body voltage into our calculations, assume the source voltage is close
to the body voltage so Vdb ~ Vds.
⚫ Hence, increasing Vds decreases the effective channel length. Shorter channel length results in
higher current; thus, Ids increases with Vds in saturation, as shown in Figure 2.18.
⚫ This can be modeled by multiplying Idsat equation by a factor of (1 + Vds / VA), where VA is
called the Early voltage.
⚫ In the saturation region, we find

⚫ As channel length gets shorter, the effect of the channel length modulation becomes relatively
more important. Hence, VA is proportional to channel length.
⚫ Channel length modulation is very important to analog designers because it reduces the gain of
amplifiers.
Threshold Voltage Effects:
Body Effect:
⚫ When a voltage Vsb is applied between the source and body, it increases the amount of charge
required to invert the channel, hence, it increases the threshold voltage. The threshold voltage
can be modeled as

where Vt0 is the threshold voltage when the source is at the body potential, Ks is the surface

potential at threshold, and ˠ is the body effect coefficient, typically in the range 0.4 to 1 V1/2.

⚫ The body effect further degrades the performance of pass transistors trying to pass the weak
value (e.g., nMOS transistors passing a ‘1’)

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⚫ For small voltages applied to the source or body,

⚫ Drain-Induced Barrier Lowering The drain voltage Vds creates an electric field that affects the
threshold voltage. This drain-induced barrier lowering (DIBL) effect is especially pronounced
in short-channel transistors. It can be modeled as

where M is the DIBL coefficient, typically on the order of 0.1

⚫ Drain-induced barrier lowering causes Ids to increase with Vds in saturation, in much the
same way as channel length modulation does.DIBL increases subthreshold leakage at
high Vds.
Short Channel Effect:
⚫ The threshold voltage typically increases with channel length.This phenomenon is especially
pronounced for small L where the source and drain depletion regions extend into a significant
portion of the channel, and hence is called the short channel effect or Vt rolloff
⚫ In some processes, a reverse short channel effect causes Vt to decrease with length. There is also
a narrow channel effect in which Vt varies with channel width; this effect tends to be less
significant because the minimum width is greater than the minimum length.
Leakage:
⚫ Even when transistors are nominally OFF, they leak small amounts of current. Leakage
mechanisms include subthreshold conduction between source and drain, gate leakage from the
gate to body, and junction leakage from source to body and drain to body, as illustrated in Figure
2.19.

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⚫ Subthreshold conduction is caused by thermal emission of carriers over the potential barrier set
by the threshold.
⚫ Gate leakage is a quantum-mechanical effect caused by tunneling through the extremely thin
gate dielectric.
⚫ Junction leakage is caused by current through the p-n junction between the source/drain
diffusions and the body
Sub threshold Leakage:
⚫ The long-channel transistor I-V model assumes current only flows from source to drain when
Vgs > Vt.
⚫ In real transistors, current does not abruptly cut off below threshold, but rather drops off
exponentially, as seen in Figure 2.20.
⚫ When the gate voltage is high, the transistor is strongly ON. When the gate falls below Vt, the
exponential decline in current appears as a straight line on the logarithmic scale.
⚫ This regime of Vgs < Vt is called weak inversion.
⚫ The subthreshold leakage current increases significantly with Vds because of drain-induced
barrier lowering.
⚫ There is a lower limit on Ids set by drain junction leakage that is exacerbated by the negative
gate voltage

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Gate Leakage:

⚫ The effect of carriers crossing a thin barrier is called tunneling, and results in leakage
current through the gate.
⚫ Two physical mechanisms for gate tunneling are called Fowler-Nordheim (FN) tunneling
and direct tunneling.
⚫ FN tunneling is most important at high voltage and moderate oxide thickness and is used
to program EEPROM memories .
⚫ Tunneling current can be an order of magnitude higher for nMOS than pMOS transistors
with SiO2 gate dielectrics because the electrons tunnel from the conduction band while
the holes tunnel from the valence band and see a higher barrier.
⚫ The direct gate tunneling current can be estimated as

⚫ Figure 2.21 plots gate leakage current density (current/area) JG against voltage for various oxide
thicknesses. Gate leakage increases by a factor of 2.7 or more per angstrom reduction in
thickness

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Junction Leakage:

⚫ The p–n junctions between diffusion and the substrate or well form diodes, as shown in Figure
2.22. The well-to-substrate junction is another diode.

⚫ The substrate and well are tied to GND or VDD to ensure these diodes do not become forward
biased in normal operation. However, reverse-biased diodes still conduct a small amount of
current ID.

where IS depends on doping levels and on the area and perimeter of the diffusion region
and VD is the diode voltage (e.g., –Vsb or –Vdb).
⚫ More significantly, heavily doped drains are subject to band-to-band tunneling (BTBT) and
gate-induced drain leakage (GIDL).

Temperature Dependence:
⚫ Transistor characteristics are influenced by temperature. Carrier mobility decreases with
temperature. An approximate relation is

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where T is the absolute temperature, Tr is room temperature, and kR is a fitting parameter

with a typical value of about 1.5. vsat also decreases with temperature, dropping by about
20% from 300 to 400 K.
⚫ The magnitude of the threshold voltage decreases nearly linearly with temperature
and may be approximated by

where kvt is typically about 1–2 mV/K.

⚫ Ion at high VDD decreases with temperature. Subthreshold leakage increases exponen
tially with temperature. BTBT increases slowly with temperature, and gate leakage is
almost independent of temperature.
⚫ The combined temperature effects are shown in Figure 2.23. At high Vgs, the current
has a negative temperature coefficient; i.e., it decreases with temperature. At low Vgs, the current
has a positive temperature coefficient.

⚫ Thus, OFF current increases with temperature. ON current Idsat normally decreases with temperature,
as shown in Figure 2.24, so circuit performance is worst at high temperature. However, for systems
operating at low VDD (typically < 0.7 – 1.1 V), Idsat increases with temperature .
Geometry Dependence:
⚫ The layout designer draws transistors with width and length Wdrawn and Ldrawn. The actual gate
dimensions may differ by some factors XW and XL.

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⚫ For example, the manufacturer may create masks with narrower polysilicon or may overetch the
polysilicon to provide shorter channels (negative XL) without changing the overall design rules or
metal pitch.
⚫ Moreover, the source and drain tend to diffuse laterally under the gate by LD, producing a shorter
effective channel length that the carriers must traverse between source and drain.
⚫ Similarly, WD accounts for other effects that shrink the transistor width. Putting these factors
together, we can compute effective transistor lengths and widths that should be used in place of L and
W in the current and capacitance equations. The factors of two come from lateral diffusion on both
sides of the channel.

⚫ Therefore, a transistor drawn twice as long may have an effective length that is more than twice as
great.
⚫ Similarly, two transistors differing in drawn widths by a factor of two may differ in saturation current
by more than a factor of two. Threshold voltages also vary with transistor dimensions because of the
short and narrow channel effects.

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DC Transfer Characteristics:
• DC transfer characteristics of a circuit relate the output voltage to the input voltage,
assuming the input changes slowly enough that capacitances have plenty of time to charge
or discharge.

CMOS Inverter Static Characteristics

Fig 1.9 CMOS Inverter

⚫ CMOS inverter shown in Fig 1.9. Table below outlines various regions of operation for the
n- and p-transistors.
⚫ In this table, Vtn is the threshold voltage of the n-channel device, and Vtp is the
threshold voltage of the p-channel device.
⚫ Note that Vtp is negative. The equations are given both in terms of Vgs/Vds and
Vin/Vout.
⚫ As the source of the nMOS transistor is grounded, Vgsn = Vin and Vdsn = Vout.
⚫ As the source of the pMOS transistor is tied to VDD,
Vgsp =Vin – VDD and Vdsp =Vout – VDD.

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• The objective is to find the variation in output voltage (Vout) as a function of the input
voltage (Vin). This may be done graphically, for simplicity, we assume Vtp = –Vtn and
that the pMOS transistor is 2–3 times as wide as the nMOS transistor so βn = βp.
• The plot shows Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and
Vgsp using drain current equation.
• Fig 1.10(b) shows the same plot of Idsn and |Idsp| now in terms of Vout for various values
of Vin. The possible operating points of the inverter, marked with dots, are the values of
Vout where Idsn = |Idsp| for same Vin.
• These operating points are plotted on Vout vs. Vin axes in Fig. (c) to show the inverter DC
transfer characteristics.
• The supply current IDD = Idsn = |Idsp| is also plotted against Vin in Fig (d) showing that
both transistors are momentarily ON as Vin passes through voltages between GND and
VDD, resulting in a pulse of current drawn from the power supply.
• The operation of the CMOS inverter can be divided into five regions indicated on Fig
1.10(c). The state of each transistor in each region and state of output is shown in Table 2.
o In region A, the nMOS transistor is OFF so the pMOS transistor pulls the output
to VDD.
o In region B, the nMOS transistor starts to turn ON, pulling the output down.
o In region C, both transistors are in saturation.
o In region D, the pMOS transistor is partially ON
o In region E, pMOS is completely OFF, leaving the nMOS transistor to pull the
output down to GND.

Table 2. Summary of CMOS Inverter Operation

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Fig 1.10 Graphical Derivation of CMOS Inverter DC Characteristics

In the fig. the crossover point where Vin = Vout, is called the ‘input
threshold’

Fig. CMOS inverter Transfer Characteristics

Beta Ratio Effects:

• We have seen that for βn = βp the inverter threshold voltage Vinv is VDD/2. This may be
desirable because it maximizes noise margins.
• Inverters with different beta ratios βp/βn are called skewed inverters. If βp/βn > 1, the
inverter is HI-skewed. If βp/βn < 1, the inverter is LO-skewed. If βp/βn = 1, the inverter
has normal skew or is unskewed.
• A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is VDD/2, we
would expect the output will be greater than VDD/2.
• LO-skew inverter has a weaker pMOS transistor and thus a lower switching threshold.
• Figure explores the impact of skewing the beta ratio on the DC transfer characteristics. As
the beta ratio is changed, the switching threshold moves. However, the output voltage
transition remains sharp. Gates are usually skewed by adjusting the widths of transistors
while maintaining minimum length for speed.

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Fig. Transfer Characteristics of Skewed Inverters

Noise Margin:

• Noise margin is closely related to the DC voltage characteristics. This parameter allows
you to determine the allowable noise voltage on the input of a gate so that the output will
not be corrupted.
• The specification most commonly used to describe noise margin (or noise immunity) uses
two parameters: the LOW noise margin, NML, and the HIGH noise margin, NMH.
• With reference to Fig1.12, NML is defined as the difference in maximum LOW input
voltage recognized by the receiving gate and the maximum LOW output voltage produced
by the driving gate.

• Similarly NMH is the difference between the minimum HIGH output voltage of the driving
gate and the minimum HIGH input voltage recognized by the receiving gate.

Where VIH = minimum HIGH input voltage

VIL = maximum LOW input voltage
VOH= minimum HIGH output voltage
VOL= maximum LOW output voltage

Fig. Noise Margin Definitions

• Inputs between VIL and VIH are said to be in the indeterminate region or forbidden zone
and do not represent any legal digital logic levels. Therefore, it is generally desirable to
have VIH as close as possible to VIL and for this value to be midway in the “logic swing,”

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VOL to VOH. This implies that the transfer characteristic should switch abruptly; that is,
there should be high gain in the transition region.
• DC analysis gives us the static noise margins specifying the level of noise that a gate may
see for an indefinite duration.

Pass Transistor DC characteristics:

• nMOS transistors pass ‘0’s well but 1s poorly. Figure (a) shows an nMOS transistor
with the gate and drain tied to VDD. Imagine that the source is initially at Vs = 0.
Vgs > Vtn, so the transistor is ON and current flows. If the voltage on the source rises
to Vs = VDD – Vtn, Vgs falls to Vtn and the transistor cuts itself OFF.
• Therefore, nMOS transistors attempting to pass a 1 never pull the source above
VDD – Vtn. This loss is sometimes called a threshold drop.
• Similarly, pMOS transistors pass 1s well but 0s poorly. If the pMOS source drops
below |Vtp|, the transistor cuts off. Hence, pMOS transistors only pull down to within
a threshold above GND, as shown in Fig (b).
• As the source can rise to within a threshold voltage of the gate, the output of several
transistors in series is no more degraded than that of a single transistor Fig (c ).
• However, if a degraded output drives the gate of another transistor, the second transistor
can produce an even further degraded output Fig(d).

Fig. Pass Transistor Threshold drop

• The problem seen with nMOS and pMOS of not passing strong 1’s and strong 0’s
respectively can be overcome by using Transmission gate.
• It has an nMOS and pMOS connected in parallel as shown in fig below.

Fig. Schematic and symbol of Transmission gate (TG)

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• When A is logic high both transistors are ON and TG is said to be ON. When
input is provided as nMOS is not able to transmit strong 1, pMOS will do the
function. Similarly when pMOS is not able to transmit strong 0, nMOS will do
this function.
• Thus transmission gate is able to send both strong 0 and strong 1 without any
signal degradation.
• Transmission gate can be used as
o Multiplexing element
o Analog switch
o Latch element

Fig. Resistance of Transmission gate as a function of input voltage

Tristate inverters:

• By cascading a transmission gate and an inverter forms a tristate inverter as shown

in Fig (a)
• When EN = 1, EN’= 0, thus transmission gate is ON and transmits the output Y as
the compliment of inverter input A.
• When EN = 0 and EN’ =1, transmission gate is OFF and the output Y is in tristate
or high impedance state.
• Fig (b) and (c) shows other configurations of tristate inverters

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Ratioed Inverters Transfer Characteristics

• Other than CMOS inverter there are also other forms of inverters. One such is
shown in the fig. below which has an nMOS with load as resistor.
• This is an nMOS inverter circuit. When Vin = 0, nMOS is OFF and output goes to
Vdd through the Rload.
• When Vin = 1, nMOS is ON and pulls the output to gnd.
• When we consider the transfer characteristics and I-V characteristics, we see that
as load is increased VOL decreases also the current decreases. Thus choosing load
resistor compromises between current and VOL.

Fig. nMOS inverter with resistive load, I-V characteristics and transfer characteristics

• An alternate to this is using a more practical circuit called pseudo-nMOS inverter

circuit, which uses a pMOS transistor as a load with its gate terminal always
grounded.
• Here pMOS will be in ON state. When Vin = 0, nMOS is OFF and as pMOS is ON
the output rises to Vdd. When Vin = 1, nMOS will be ON and pulls the output to
gnd.
• When the transfer characteristics is observed as the W/L ratio is varied for pMOS
in the pseudo-nMOS inverter circuit, the shape of the transfer characteristics varies.
• As parameter P (i.e., as W is decreased sharper characteristics is obtained) is varied
characteristics varies with higher value of P less sharper characteristics is seen.
• In the circuit P/2 represents the W/L ratio.

Fig. pseudo-nMOS inverter with I-V characteristics and transfer characteristics

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• These types of gates are called as ratioed circuits as transfer function depends on
the strength of pull down (pMOS) to pull up (nMOS) devices.
• In these types of circuits ratios must be chosen properly so that circuit operates
properly.
• Disadvantage seen with these ratioed circuits are
o Constant power dissipation
o Poor noise margin
• However these circuits are used under limited circumstances such as reduced input
capacitance and smaller area.

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