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Intel 8085 microprocessor architecture

microprocessor architecture

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8 views

Intel 8085 microprocessor architecture

microprocessor architecture

Uploaded by

AmitavaNandi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Intel 8085 microprocessor architecture

Intel 8085 microprocessor architecture

Memory

Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB.

Program memory - program can be located anywhere in memory. Jump, branch and call instructions use 16-bit
addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute
addressing.

Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere.

Stack memory is limited only by the size of memory. Stack grows downward.

First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.

Interrupts

The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):

INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one
instruction, usually one of these instructions:

● One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and
branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
● CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second
and third bytes of the instruction.

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into
stack and branches to 2Ch (hexadecimal) address.

RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into
stack and branches to 34h (hexadecimal) address.

RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into
stack and branches to 3Ch (hexadecimal) address.

Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into
stack and branches to 24h (hexadecimal) address.

All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts
can be enabled or disabled individually using SIM instruction.

I/O ports

256 Input ports


256 Output ports

http://www.cpu-world.com/Arch/8085.html (1 of 2)2/3/2005 11:16:03 AM


Intel 8085 microprocessor architecture

Registers

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.

Flag is an 8-bit register containing 5 1-bit flags:

● Sign - set if the most significant bit of the result is set.


● Zero - set if the result is zero.
● Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
● Parity - set if the parity (the number of set bits in the result) is even.
● Carry - set if there was a carry during addition, or borrow during subtraction/comparison.

General registers:

● 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register
contains low-order byte. Some instructions may use BC register as a data pointer.
● 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register
contains low-order byte. Some instructions may use DE register as a data pointer.
● 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains
low-order byte. HL register usually contains a data pointer used to reference memory addresses.

Stack pointer is a 16 bit register. This register is always incremented/decremented by 2.

Program counter is a 16-bit register.

Instruction Set

8085 instruction set consists of the following instructions:

● Data moving instructions.


● Arithmetic - add, subtract, increment and decrement.
● Logic - AND, OR, XOR and rotate.
● Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts.
● Input/Output instructions.
● Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

Addressing modes

Register - references the data in a register or in a register pair.


Register indirect - instruction specifies register pair containing address, where the data is located.
Direct.
Immediate - 8 or 16-bit data.

Last modified: 4 Jan 2005

All microprocessor architectures

(c) Copyright 2003 Gennadiy Shvets

http://www.cpu-world.com/Arch/8085.html (2 of 2)2/3/2005 11:16:03 AM

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