Combinational Logic Circuits

BASIC ADDERS
The Half-Adder

Half-Adder Logic
BASIC ADDERS
The Full-Adder
The full-adder accepts two input bits and an input carry and generates a sum output and an
output carry.

Full adder Logic

Using min term method

BASIC ADDERS
The Full-Adder
PARALLEL BINARY ADDERS
Two or more full-adders are connected to form parallel binary adders.
 PARALLEL BINARY ADDERS
Four-Bit Parallel Adders
A group of four bits is called a nibble. A basic 4-bit parallel adder is implemented
with four full-adder stages as shown in Figure
 Truth Table for a 4-Bit Parallel Adder

The subscript n represents the adder bits and can be I, 2, 3, or 4 for the 4-bit adder.
Example:
 ENCODERS

• The process of Converting familiar symbols or numbers into a coded format.

• An encoder accepts an active level on one of its inputs representing a digit, such as a
decimal or octal digit, and converts it to a coded output, such as BCD or binary.
• Encoders can also be devised to encode various symbols and alphabetic characters.

Eight-To-Three Line Encoders (Octal-to-Binary)

Eight-To-Three Line Encoders (Octal-to-Binary)

C=4+5+6+7
B=2+3+6+7
A=1+3+5+7
The Decimal-to-BCD Encoder (Ten-To-Four Encoder)

The most significant bit of the BCD code, A 3 , is always a 1 for decimal digit 8 or 9.
An OR expression for bit A3 in terms of the decimal digits can therefore be written
as
The Decimal-to-BCD Encoder (Ten-To-Four Encoder)
An Application
 DECODERS

• Performs Reverse of Encoders

• A decoder is a digital circuit that detects the presence of a specified combination of bits
(code) on its inputs and indicates the presence of that code by a specified output level.

• A decoder has n input lines to handle n bits and from one to 2n output lines to indicate the
presence of one or more n-bit combinations.
The Basic Binary Decoder
Example for the decoding of 1001
DECODERS
 A3 A2 A1 A0
The BCD-to-Decimal Decoder

0
1
2
3
4
5
6
7
8
9
The 4-Bit Decoder
Example

For 4-to-16 Decoder

 MULTIPLEXERS (DATA SELECTORS)
• A multiplexer (MUX) is a combinational circuit that selects one input from multiple inputs and
forwards it to a single output line based on selection inputs.

• The basic multiplexer has several data-input lines and a single output line.

• Purpose: Used to route one of several input signals to a single output.

• It also has data-select inputs. which permit digital data on anyone of the inputs to be switched to
the output line.

• Multiplexers are also known as data selectors.

• Applications: Data selection, signal routing, and communication systems.

The Basic 2-line to 1-line MUX

 MULTIPLEXERS (DATA SELECTORS)

• Components: Inputs (Data lines), select lines, and output.

• Selection Mechanism: Based on the binary value of select lines, one input is routed to the
output.

• Example: 4-to-1 MUX has 4 data inputs, 2 select lines, and 1 output.

Logic symbol for a 1-of-4 data selector/multiplexer.

 MULTIPLEXERS (4-to-1 MUX )

The logic circuitry required to perform this multiplexing

operation→

Because data can be selected from anyone of the input lines, this circuit is also referred to as a data selector.
MULTIPLEXERS (8 Input or 1-of-8 Multiplexers)

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+

S0'.S1.S2 .A6+S0.S1.S3.A7

A0
A1
A2
A3
A4
A5
A6
A7
 MULTIPLEXERS

Applications:
• Data Routing: Used in communication systems to route data.

• Control Systems: Selects between control signals based on control conditions.

• The seven Segment Display Multiplexer

• Digital counters with multiplexed displays

• Parallel-to-serial conversion
 DEMULTIPLEXERS

• A demultiplexer (DEMUX) basically reverses the multiplexing function.

• It takes digital information from one line and distribute it to a given number of output lines.

• For this reason, the demultiplexer is also known as a data distributor.

• Purpose: Used to distribute a single data line to multiple outputs.

• Applications: Data distribution, communication systems, memory address decoding.

The 1 to 2 Line Demultiplexer

 Structure of a Demultiplexer

One-To-Four Line Demultiplexer

D0=S1’S0’I
D1=S1’S0I
D2=S1S0’I
D3=S1S0I
1-line-to-16-line Demultiplexer
1-line-to-16-line decoder
 Comparison Between MUX and DEMUX

• Multiplexer: Selects one of multiple inputs and routes it to a single output.

• Demultiplexer: Takes a single input and routes it to one of multiple outputs.

MUX

DEMUX
 Why do we study sequential logic??
• Why not only combinational logic?

• We can build complex circuits: adder, multiplier etc.

• However there are many applications in which digital outputs are required to be generated
in accordance with the sequence in which the input signals are received, which cannot be
accomplished using combinational circuits.

• These applications require outputs to be generated, they are not only dependent on the
level present at the inputs at that time, but also on the state of circuit. i.e. on the prior input
level conditions.

• But… real-world problems are sequential in time

• We want to build systems that step through computations

• These systems have memory and feedback. The past history is provided by feedback from

• The output fed back to the input.

• They use sequence of inputs to transition from state to state

 Recall: Combinational vs. sequential systems

• A simple model of a digital system is a unit with inputs and outputs:

inputs system outputs

• Combinational systems are "memory-less"

• The outputs depend only on the present inputs
• Sequential systems have memory
• The output values depend on the input values and previous input values

inputs output
s
Comparison of Combinational and Sequential Logic circuits
 synchronous and asynchronous sequential circuits

The sequential circuits are classified as synchronous sequential circuits and asynchronous
sequential circuits depending on the timing of their signals.
(i) Synchronous Sequential Circuit
• The change in input signals can affect memory element upon activation of clock signals.
• The maximum operational speed of clock depends on time delays involved.
• In this circuit, memory elements are "clocked flip-flops",
• It is easier to design.
• It is generally "edge triggered".
(ii) Asynchronous Sequential Circuit
• The change in input signals can affect memory element at any instant of time.
• Because of absence of clock, this circuit can operate faster than synchronous circuit.
• In this circuit, memory elements are either "un-clocked flip-flops" or time delay elements.
• More difficult to design.
• It is generally "Level triggered".
 synchronous and asynchronous sequential circuits
The sequential circuits are classified as synchronous sequential circuits and asynchronous sequential
circuits depending on the timing of their signals.
(i) Synchronous Sequential Circuit
• Definition: Circuits where all state changes are synchronized with a clock signal.
• The maximum operational speed of clock depends on time delays involved.
• In this circuit, memory elements are "clocked flip-flops",
• It is easier to design.
• Key Features: Changes occur only at clock edges (rising or falling).
Predictable timing due to clock synchronization.
• Examples: Counters, Shift Registers, Finite State Machines
(ii) Asynchronous Sequential Circuit
• Definition: Circuits where state changes occur independently of a clock signal..
• Key features: Because of absence of clock, this circuit can operate faster than synchronous circuit.
Less predictable due to varying signal propagation times.
• In this circuit, memory elements are either "un-clocked flip-flops" or time delay elements.
• Examples: Ripple Counters, Priority Encoders
 Triggering

Triggering refers to the mechanism that causes a flip-flop or circuit to respond to a clock signal. Its
main purpose is to synchronize latches or flip-flops.
It is classified as: (i) Level triggering (ij) Edge triggering
i) Definition: The circuit responds to the clock signal as long as it remains at a specific level (HIGH or LOW).
Types:
Positive Level Triggering: Responds when the clock is
HIGH (logic 1).
Negative Level Triggering: Responds when the clock is
LOW (logic 0).

ii) Definition: The circuit responds only at the transition of the clock signal.
Types:
Positive Edge Triggering: Triggered on the rising edge (LOW
to HIGH transition).
Negative Edge Triggering: Triggered on the falling edge
(HIGH to LOW transition).

In level triggering circuit the output may change several times in a single clock, whereas in edge
triggering circuit the output will change only once in a single clock.
 LATCHES and FLIP-FLOPS

Latch is a type of temporary storage device.

• Latch is a basic sequential logic circuit that can store one bit of information.
• It has two stable states (bistable) and is normally placed in a category separate from that of flip-
flops.
• A flip-flop, known more formally as a bistable multivibrator, has two stable states. It can remain in
either of the states indefinitely, and the state can be changed by, applying proper triggering signal.
• The main difference between latches and flip-flops is in the method used for changing their state.

Ex: SR (Set-Reset) Latch, D (Data) Latch Ex: SR Flip-Flop, JK Flip-Flop, D Flip-Flop, T (Toggle) Flip-Flop
 The S-R Latch

Set-Reset Latch.
A bistable circuit with Set (S) and Reset (R) inputs used to store a single bit.
It can be constructed with two cross coupled NAND gates or two cross-coupled NOR gates
• The two inputs labeled S for set and R for reset. Inputs:
ത.
• The two outputs are Q and 𝑄 𝑆: Sets the output to 1.
𝑅: Resets the output to 0.

Outputs:
𝑄: Main output.
𝑄​ത : Complementary output.
The S-R Latch- Using NAND gate
SR Latch
 Clocked Flip-Flop

Digital systems can operate either Asynchronously or Synchronously.

• In synchronous system, the exact time at which any output can change states is determined by a
signal commonly known as the "Clock signal".
• The outputs can change states only when the clock makes a transition (also called edges).
• Clock changes from 0 to 1 ~ Positive going transition (PGT).
• Clock changes from 1 to 0 ~ Negative going transition (NGT).

• Clocked FFs have a clock input i.e. typically labelled CLK, CK or CP.
• This is indicated by a small triangle on the CLK input.
• The active transition at the CLK inputs triggers the change or the CLK input determines the "When“
to change.
Clocked S-R Flip-Flop

SR Using NOR SR Using NAND

OR
Clocked S-R Flip-Flop- Positive edge triggered
Clocked S-R Flip-Flop- Positive edge triggered-Timing Diagram
 D Flip Flop

• From the truth table of S-R flip flop it is clear that the output of S-R flip-flop is in unpredictable state
when the inputs are same (ie. when S = R = 0 then Q = Halt and when S = R = 1; Q = invalid).
• Therefore in many practical applications, these input conditions are not required.
• Thus the modified S-R flip flop in which such conditions are avoided is known as D-flip flop
• It Is a flip-flop with delay equal to exactly one cycle of CLK.
• It is also called "data transmission flip-flop". and "transparent latch".
Timing Diagram – D flip flop
 J-K Flip-Flop

• The J-K flip-flop is a refinement of the S-R flip-flop in which the indeterminate (invalid) state
of the S-R type is redefined in the J-K type (S=1 and R=1).
• The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop.

• In J-K flip-flop the data input J and K ANDed with Q and 𝑄ത respectively to obtain S and R inputs
i.e.

𝑄ത

Q
 J-K Flip-Flop- Detailed Analysis

S
𝑄ത

R
Q

J K Qn 𝑄𝑛 S R Qn+1 𝑄𝑛 + 1
1 1 1 0 0 1 0 1
1 1 0 1 1 0 1 0
0 1 1 0 0 1 0 1
0 1 0 1 0 0 0 1 Previous state
1 0 1 0 0 0 1 0 Previous state
1 0 0 1 1 0 1 0
0 0 1 0 0 0 Hold
0 0 0 1 0 0 Hold
Timing Diagram- J-K Flip flop
 Race Around Condition

The "Race around condition" will occur when

(i) J = K = 1

(ii) When tpd (FF) < tpW

(iii) When level trigger is applied.

To avoid Race around Condition in J K Flip flop, we use

Master- Slave Configuration
 Master-Slave Flip-Flop

• A "M-S FF" is basically constructed from

2 FFs (a MASTER and a SLAVE) and an 'INVERTER’.
• On the rising edge of CLK (ie. +ve edge CLK PULSE) the control
inputs are used to determine the output of the "MASTER".
• When the ClK goes LOW (Le. -ve edge CLK PULSE), the state of
Master is transferred to the "SLAVE", whose outputs are Q and
Q’.
• In the "M-S FF", output is fully dependent upon the output of
SLAVE-FF. Logic Diagram of M-S FF
 Master-Slave Flip-Flop

Operation

• When clock pulse CLK is 0, the output of the inverter is 1.

• Since the clock input of the slave is 1 the flip-flop is enabled and output Q is
equal to Y, while Q is equal to if.
• The master flip-flop is disabled because CLK = O.
• When the Clock pulse becomes 1, .the information at the external R and S
inputs is transmitted to the master flip-flop. Logic Diagram of M-S FF
• The slave flip-flop, however, is isolated as long as the pulse is at its level 1
because the output of the inverter is O.
• When pulse returns to 0, the master flip-flop is isolated, Which prevents
the external inputs from affecting It.
• The slave flip-flop then goes to the same state as the master flip-flop.
 Master-Slave Flip-Flop

Master-Slave J-K Flip-Flop by using only NAND gates

Master Slave

Timing diagram in M-S FF

J
 Applications of FF-Counters

Introduction to Counters
Definition: A counter is a sequential circuit that counts the number of occurrences of input signals.

Applications: Digital clocks, frequency counters, event counters, etc.

Types: Synchronous and Asynchronous.

➢ Each count, a binary number is called a state of a counter. Hence, a counter counting in
terms of n-bits (n flip-flops) has 2n different states.
➢ The number of different states in counting sequence is also known as the modulus of
the counter.
➢ Thus, for n-flip-flops counter will have '2n' different states and then the counter is said
to be "MOD-2n" counter.
 Applications of FF-Counters

Introduction to Counters

Counters are classified into two broad categories according to the way they are clocked:
asynchronous and synchronous.

In asynchronous counters, commonly called ripple counters, the first flip-flop is clocked
by the external clock pulse and then each successive flip-flop is clocked by the output of the
preceding flip-flop.

In synchronous counters, the clock input is connected to all of the flip-flops so that they
are clocked simultaneously.
Within each of these two categories, counters are classified primarily by
the type of sequence, the number of states, or the number of flip-flops in the counter.
 Asynchronous Counters

Definition: Counters where flip-flops are triggered by the output of the previous flip-flop, not by a
common clock signal.
Also known as ripple counters; clock signal is not common to all flip-flops.
Advantages: Simple design, fewer components.
Disadvantages: Propagation delay accumulates.
Examples:
Binary Counter: Counts in binary (e.g., 0000 → 0001 → 0010).
Decade Counter: Counts from 0 to 9 (0000 to 1001 in binary).
Applications of Asynchronous Counters Examples: Frequency division, Digital clocks, Timers,
Event counting.
How Asynchronous Counters Work: Basic Concept: Each flip-flop toggles when the preceding flip-
flop changes from 1 to 0 (Negative edge /falling edge triggering) or 0 to 1 (positive edge triggering).
 2-Bit Asynchronous Binary Counter

Components:
• Two flip-flops (e.g., T flip-flops or JK flip-flops in toggle mode).
• Clock input is applied to the first flip-flop only.
 2-Bit Asynchronous Binary Counter

Components:
• Two flip-flops (e.g., T flip-flops or JK flip-flops in toggle mode).
• Clock input is applied to the first flip-flop only.

The Timing Diagram

A 3-Bit Asynchronous Binary Counter
4-bit asynchronous binary counter
 Asynchronous Decade Counters or BCD decade counter
(Truncated sequence counters)
Truncated sequence counters- A counter with modulus less than 2n

Definition: A counter that counts from 0 to 9 (mod 10 counter) and resets to 0 after the 10th pulse.
(or 0000 to 1001)

Components: Four flip-flops. Additional AND gate logic for reset after count 9.
Asynchronous Decade Counters

An asynchronously clocked
decade counter with
asynchronous recycling.
 Synchronous Counters

A synchronous counter is one in which all the flip-flops in the counter are
clocked at the same time by a common clock pulse.

2-Bit Synchronous Binary Counter

Timing diagram for the counter

 Synchronous Counters

3-Bit Synchronous Binary Counter

Timing diagram for the counter

4-Bit Synchronous Binary Counter

Timing diagram for the counter

4-Bit Synchronous Binary Counter
 4-Bit Synchronous Decade Counter (synchronous BCD decade counter )

• a BCD decade counter exhibits a truncated binary sequence and goes from 0000
through the 1001 state.

• Rather than going from the 1001 state to the 1010 state, it recycles to the 0000
state.
Logic of 4-Bit Synchronous Decade Counter
Logic of 4-Bit Synchronous Decade Counter
 4-Bit Synchronous Decade Counter (synchronous BCD decade counter )

States of a BCD decade counter.

 Shift Registers

• Shift registers are a type of sequential logic circuit.

• Shift registers consist of arrangements of flip-flops and are important in applications involving the
storage and transfer of data in a digital system.
• A register. unlike a counter, has no specified sequence of states.
• A register, in general, is used solely for storing and shifting data (1s and 0s) entered into it from an
external source.
• The storage capability of a register makes it an important type of memory device.

• Figure illustrates the concept of storing a 1 or a 0 in a D flip-flop.

Shift Registers

1. SISO 2. SIPO 3. PISO 4. PIPO

 SERIAL IN/SERIAL OUT SHIFT REGISTERS

❖ The serial in/serial out shift register accepts data serially-that is, one bit at a time on
a single line.
❖ It produces the stored information on its output also in serial form.
SERIAL IN/SERIAL OUT SHIFT REGISTERS

Procedure for Four bits (1010) being entered serially into the register.
 SERIAL IN/SERIAL OUT SHIFT REGISTERS

Four bits (1010) being serially shifted out of the register and replaced by all zeros.
 SERIAL IN/PARALLEL OUT SHIFT REGISTERS (SIPO)

❖ Data bits are entered serially (right-most bit first) into this type of register.
❖ The difference is how the data bits are taken out of the register in the parallel output register, the
output of each stage is available.
❖ Once the data are stored, each bit appears on its respective output line, and all bits are available
simultaneously, rather than on a bit-by-bit basis as with the serial output.
SERIAL IN/PARALLEL OUT SHIFT REGISTERS (SIPO)
 PARALLEL IN/PARALLEL OUT SHIFT REGISTERS (PIPO)

❖ The parallel in/parallel out register employs Parallel input and Parallel Output.
❖ Immediately following the simultaneous entry of all data bits, the bits appear on the
parallel outputs.
 Integrated Circuit technologies-CMOS and TTL

CMOS (Complementary Metal-Oxide-Semiconductor)

Working Principle:
•CMOS uses complementary pairs of MOSFETs (P-type and N-type
transistors) to achieve logic operations.
Static Operation:
• When idle, only one of the transistors (either P-MOS or N-MOS) conducts,
resulting in negligible static power consumption.
Logic States:
•Logic HIGH: P-MOS is OFF, N-MOS is ON.
•Logic LOW: P-MOS is ON, N-MOS is OFF.

Applications of CMOS:
•Consumer Electronics: Used in microprocessors, memory chips, and digital
logic circuits for devices like smartphones, laptops, and digital cameras.
•Battery-Powered Devices: Preferred for low-power applications such as
calculators and watches.
 Integrated Circuit technologies-CMOS and TTL

TTL (Transistor-Transistor Logic)

Working Principle:
•TTL circuits use bipolar junction transistors (BJTs) as the primary
switching elements.
Static Operation:
• Base-emitter junction of transistors determines the logic levels.
• Transistors either saturate or cutoff to represent HIGH and LOW states.
Logic States: TTL Inverter
• Logic HIGH: Transistor in cutoff state.
• Logic LOW: Transistor in saturation state.
Applications of TTL:
•Industrial Control Systems: TTL circuits are widely used in automation and
control hardware.
•High-Speed Logic Circuits: Due to faster switching speeds, TTL is used in
timing-sensitive applications.
Difference between CMOS and TTL
 Basic Operational characteristics and Parameters of CMOS and TTL

DC Power Supply
•CMOS:
Operates over a wide voltage range (typically 3V to 15V). The low power consumption
makes CMOS ideal for battery-powered applications (+ 5 V, + 3.3 V, 2.5 V, and 1.2 V).
•TTL:
Standard TTL circuits require a regulated 5V power supply. Modern TTL variants (e.g.,
TTL-LS) have slight flexibility in voltage.
 Basic Operational characteristics and Parameters of CMOS and TTL

CMOS Logic Levels

There are four different logic-level specifications: VIL, VIH , VOL, and VOH
• For CMOS circuits, the ranges of input voltages (VILthat can represent a valid
LOW (logic 0) are from 0 V to 1.5 V for the +5 V.
• The ranges of input voltages (VIH ) that can represent a valid HIGH (logic 1)
are from 3.5 V to 5 V for the 5 V.
• The ranges of values from 1.5 V to 3.5 V for 5 V logic and 0.8 V to 2 V for 3.3
V logic are regions of unpredictable performance, and values in these ranges
are unallowed.
• When an input voltage is in one of these ranges. it can be interpreted as
either a HIGH or a LOW by the logic circuit.
• Therefore, CMOS gates cannot be operated reliably when the input voltages
are in these unallowed ranges.
 Basic Operational characteristics and Parameters of CMOS and TTL

CMOS Logic Levels

The ranges of CMOS output voltages (VOL and VOH)

Notice that the minimum HIGH out put voltage VOH min is greater
than the minimum HIGH input voltage VHI min
 Basic Operational characteristics and Parameters of CMOS and TTL

TTL logic levels

Just as for CMOS. there are four different logic level specifications: VIL , VIH, VOL, and VOH
 Basic Operational characteristics and Parameters of CMOS and TTL

CMOS Logic Levels

•CMOS High (Logic 1): Close to the power supply voltage (e.g., 5V).
•CMOS Low (Logic 0): Close to ground (e.g., 0V).
CMOS logic levels are symmetric around the supply voltage, ensuring high noise margin.

TTL Logic Levels

•TTL High (Logic 1): Typically 2.7V to 5V.
•TTL Low (Logic 0): 0V to 0.8V.
TTL voltage levels are less symmetric than CMOS, and the high level is constrained to a narrower range.
 Basic Operational characteristics and Parameters of CMOS and TTL

Noise Immunity

• Noise is unwanted voltage that is induced in electrical circuits and can present a threat to the proper
operation of the circuit.
• Wires and other conductors within a system can pick up stray high-frequency electromagnetic radiation from
adjacent conductors in which cunents are changing rapidly or from many other sources external to the
system. Also, power-line voltage fluctuation is a form of low-frequency noise.
• In order not to be adversely affected by noise, a logic circuit must have a certain amount of noise immunity.
This is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs without changing
its output state.
• For example. if noise voltage causes the input of a 5 V CMOS gate to drop below 3.5 V in the HIGH state, the
input is in the unallowed region and operation is unpredictable.
• Thus, the gate may interpret the fluctuation below 3.5 V as a LOW level, as illustrated in Figure
 Basic Operational characteristics and Parameters of CMOS and TTL

Noise Immunity
•CMOS: CMOS devices have better noise immunity due to their wider noise margins and
high impedance inputs.
•TTL: TTL devices have lower noise immunity compared to CMOS because of their narrower
voltage levels and higher input currents.
 Basic Operational characteristics and Parameters of CMOS and TTL

Noise Margin
A measure of a circuit's noise immunity is called the noise margin, which is expressed in
volts.
Definition: Difference between the expected logic levels and noise threshold.
There are two values of noise margin specified
for a given logic circuit: the HIGH- level noise
margin (VNH ) and the LOW-level noise margin
(VNL ).

CMOS:
•High noise margin (~1V or more).
•Makes CMOS circuits more robust.

TTL:
•Low noise margin (~0.4V).
•Susceptible to noise interference.
 Basic Operational characteristics and Parameters of CMOS and TTL

Power Dissipation
A logic gate draws current from the dc supply volt
When the gate is in the HIGH output state,
an amount of current designated by lCCH is drawn;
and in the LOW output state. a different amount of
current. lCCL

As an example, if ICCH is specified as 1.5 mA when VCC is 5 V and if the gate is in a static
(nonchanging) HIGH output state. the power dissipation (PD) of the gate is

P D = VCClCCL = (5 V)(1.5 mA) = 7.5 mW

 Basic Operational characteristics and Parameters of CMOS and TTL

Power Dissipation

CMOS:
•Low static power dissipation; current flows only during switching.
•Ideal for power-sensitive applications.
TTL:
•High power dissipation due to continuous current flow in static conditions.
•Higher thermal output.
Title
Comparison of basic parameter of CMOS and TTL
Title
Title
Title
Title
Title
Title
Title