UC1572

UC2572
UC3572
Negative Output Flyback Pulse Width Modulator
FEATURES DESCRIPTION
• Simple Single Inductor Flyback PWM The UC3572 is a negative output flyback pulse width modulator which con-
for Negative Voltage Generation verts a positive input voltage to a regulated negative output voltage. The
chip is optimized for use in a single inductor negative flyback switching con-
• Drives External PMOS Switch
verter employing an external PMOS switch. The block diagram consists of
• Contains UVLO Circuit a precision reference, an error amplifier configured for voltage mode opera-
tion, an oscillator, a PWM comparator with latching logic, and a 0.5A peak
• Includes Pulse-by-Pulse Current Limit
gate driver. The UC3572 includes an undervoltage lockout circuit to insure
• Low 50µA Sleep Mode Current sufficient input supply voltage is present before any switching activity can
occur, and a pulse-by-pulse current limit. Output current can be sensed and
limited to a user determined maximum value. The UVLO circuit turns the
chip off when the input voltage is below the UVLO threshold. In addition, a
sleep comparator interfaces to the UVLO circuit to turn the chip off. This re-
duces the supply current to only 50µA, making the UC3572 ideal for battery
powered applications.

BLOCK DIAGRAM

UDG-94094-2

SLUS275A - MARCH 1999 - REVISED AUGUST 2001

 UC1572
UC2572
UC3572
ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V
EAINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC DIL-8, SOIC-8 (TOP VIEW)
IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA D, N or J Packages
RAMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
CS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7A to 0.7A
I3VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15mA
Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of packages.

ORDERING INFORMATION
TEMPERATURE RANGE PACKAGE
UC1572 –55°C to +125°C J
UC2572 –40°C to +85°C D, N or J
UC3572 0°C to +70°C D or N

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Reference Section
3VREF 2.94 3 3.06 V
Line Regulation VCC = 4.75 to 30V 1 10 mV
Load Regulation I3VREF = 0V to –5mA 1 10 mV
Oscillator Section
Frequency VCC = 5V to 30V 85 100 115 kHz
Error Amp Section
EAINV EAOUT = 2V –10 0 10 mV
IEANV = –1mA –0.2 –0.9 V
IEAINV EAOUT = 2V –0.2 –1.0 A
AVOL EAOUT = 0.5V to 3V 65 90 dB
EAOUT High EAINV = –100mV 3.6 4 4.4 V
EAOUT Low EAINV = 100mV 0.1 0.2 V
IEAOUT EAINV = –100mV, EAOUT = 2V –350 –500 µA
EAINV = 100mV, EAOUT = 2V 7 20 mA
Unity Gain Bandwidth TJ = 25°C, F = 10kHz 0.6 1 MHz
Current Sense Comparator Section
Threshold 0.185 0.205 0.225 V
Input Bias Current CS = 0 –0.4 –1 µA
CS Propogation Delay 300 nS

2
 UC1572
UC2572
UC3572

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Gate Drive Output Section
OUT High Saturation IOUT = 0 0 0.3 V
IOUT = –10mA 0.7 1.5 V
IOUT = –100mA 1.5 2.5 V
OUT Low Saturation IOUT = 10mA 0.1 0.4 V
IOUT = 100mA 1.5 2.2 V
Rise Time TJ = 25°C, CLOAD = 1nF + 3.3 Ohms 30 80 nS
Fall Time TJ = 25°C, CLOAD = 1nF + 3.3 Ohms 30 80 nS
Pulse Width Modulator Section
Maximum Duty Cycle EAINV = +100mV, VCC = 5V to 30V 92 96 %
Minimum Duty Cycle EAINV = –100mV, VCC = 5V to 30V 0 %
Modulator Gain EAOUT = 1.5V to 2.5V 45 55 65 %/V
Undervoltage Lockout Section
Start Threshold 3.5 4.2 4.5 V
Hysteresis 100 200 300 mV
Sleep Mode Section
Threshold 1.8 2.2 2.6 V
Supply Current Section
IVCC VCC = 5V, 30V 9 15 mA
VCC = 30, CS = 3V 50 150 A

UDG-94095

Figure 1. Typical waveforms.

3
 UC1572
UC2572
UC3572

PIN DESCRIPTIONS
3VREF: Precision 3V reference. Bypass with 100nF ca- OUT: Gate drive for external PMOS switch connected
pacitor to GND. between VCC and the flyback inductor. OUT drives the
gate of the PMOS switch between VCC and GND.
CS: Current limit sense pin. Connect to a ground refer-
enced current sense resistor in series with the flyback in- RAMP: Oscillator and ramp for pulse width modulator.
ductor. OUT will be held high (PMOS switch off) if CS Frequency is set by a capacitor to GND by the equation
exceeds 0.2V. 1
F=
EAINV: Inverting input to error amplifier. Summing junc- 15k • CRAMP
tion for 3VREF and VOUT sense. The non-inverting input
Recommended operating frequency range is 10kHz to
of the error amplifier is internally connected to GND. This
200kHz.
pin will source a maximum of 1mA.
VCC: Input voltage supply to chip. Range is 4.75 to 30V.
EAOUT: Output of error amplifier. Use EAOUT and EAINV
for loop compensation components. Bypass with a 1µF capacitor.

GND: Circuit Ground.

VIN

RSLEEP3
SLEEP 1MEG

MSLEEP
CVCC CIN
10µF UC1572 10µF
4 VCC
C3V REF OUT 5
100nF MSWITCH
8 3VREF
CRAMP
680pF
RSLEEP1
RREF 7 RAMP 56k

1 EAINV LFLYBACK

RCOMP
2 EAOUT RSLEEP2 DFLYBACK
CCOMP 33k
CS 3
6 GND
RCS
GND GND

–12V OUT
RV SENSE COUT
40k 100µF
VOUT

UDG-99057

Figure 2. Typical application: +5V to –12V flyback converter.

4
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UC2572D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UC2572D

UC2572DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UC2572D

UC2572DTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UC2572D

UC3572D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UC3572D

UC3572DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UC3572D

UC3572DTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 UC3572D

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC2572DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UC3572DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2572DTR SOIC D 8 2500 340.5 336.1 25.0
UC3572DTR SOIC D 8 2500 340.5 336.1 25.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UC2572D D SOIC 8 75 507 8 3940 4.32
UC2572DG4 D SOIC 8 75 507 8 3940 4.32
UC3572D D SOIC 8 75 507 8 3940 4.32
UC3572DG4 D SOIC 8 75 507 8 3940 4.32

Pack Materials-Page 3
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