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Cmos Problems

The document contains a series of problems related to CMOS technology, focusing on calculations involving gate oxide capacitance, transconductance, current in nFETs and pFETs, and the effects of various parameters on device performance. It covers topics such as device dimensions, mobility, threshold voltage, and the impact of parasitic resistances. Additionally, it includes inverter design and performance analysis, including midpoint voltage and timing characteristics under different load conditions.

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60 views4 pages

Cmos Problems

The document contains a series of problems related to CMOS technology, focusing on calculations involving gate oxide capacitance, transconductance, current in nFETs and pFETs, and the effects of various parameters on device performance. It covers topics such as device dimensions, mobility, threshold voltage, and the impact of parasitic resistances. Additionally, it includes inverter design and performance analysis, including midpoint voltage and timing characteristics under different load conditions.

Uploaded by

viratkholi1876rcb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CHAPTER-6

1. A CMOS process produces gate oxides with a thickness of t ox


=100Å.The FET carrier mobility values are given as µ n =550
cm2/V-sec and µp =210 cm20V-sec.
(a) Calculate the oxide capacitance per unit area in units of
fF/µm2.
(b) Find the transconductance values of nFETs and pFETs.

Place your answer in units of µA/V 2.

2. An nFET with W=10µm and L=0.35µm is built in a process


where K’n =110µA/V2 and VTn =0.70V.Assume VSBn
=0V.
(a)Find the current if the voltages are set to be V GSn=2V ,VDSn
=1.0V.
(b)Find the current if the voltages are set to be V GSn=2V ,VDSn
=2V.

3. An nFET has a device transconductance of βn =2.3 mA/V2 and a


threshold voltage of 0.76 V,Assume VSBn =0V.

(a)Find the current if the voltages are set to be


VGSn=1V ,VDSn =2.5V.

(b)Find the current if the voltages are set to be


VGSn=2V ,VDSn =2.5V.

(c)Find the current if the voltages are set to be


VGSn=3V ,VDSn =2.5V.

4. Consider a pFET that has a gate oxide thickness of t ox=60Å. The


hole mobility is measured to be 220 cm2/V-sec, and the aspect
ratio is (W/L)=(12/1). Assume that VDD=3.3V and IVTpI =0.7V.

(a) Calculate the process transconductance k’ p in units of mA/V2.

(b) Find the device transconductance βp and the resistance Rp.


5. An nFET has a gate oxide with the thickness of t ox=120Å. The p-
type bulk region is doped with the boron at a density of N a=8 x
1014cm-3. It is given that VTOn=0.55V and (W/L)=10.

(a) calculate the body bias coefficient ϒ

(b) What is the device threshold voltage if the body bias voltage
of VSBn=2V is applied?

(c) The electron mobility is µn=540 cm2/Vsec. Calculate the drain


current with the bias voltage of VGSn=3V, VDSn=3V and VSBn=3V
applied to the device.

6. Construct an RC switch model for the FET layout in the fig given
below. Assume a power supply voltage of 3V and that the
dimensions are in units of microns.

L’=0.5µm K’n=150µA/V2

Lo=0.05µm COX =2.70fF/ µm2

VTon=0.6V Cj=0.86 fF/ µm2

C jsw=0.24 fF/
µm.

7.Consider the FET geometry as


shown in fig P6.1 where the sheet resistance of n+ regions is
30Ω,and the poly gate has a sheet resistance of 26Ω.Compute
parasitic resistances Rn+ and Rpolyassociated with these
parameters by determining the appropriate geometry that applies
for each. How would these parasitics affect the device operation ?

8.AnnFET with W=20µm and L=.5µm is built in a process where


Kn’=120µA/V2 and Vtn=.65V.The voltages are set to a value of
VGSn=VDSn=VDD=5V.
a.Is the transistor saturated or non- saturated?

b.Calculate the drain source resistance using proper equation for


transistor?

c. Compare your value in (b) with that found using the equation
6.71 with the value of ŋ=1.

9.An nFET with L=.5µm is built in a process where K n’=100µA/V2


and Vtn=.70V.The gate source voltages is set to a value of
VGSn=VDD=3.3V.calculate the required channel width to obtain a
resistance of Rn=950Ω using equation (6.71) with the value of
ŋ=1.

CHAPTER-7

1.) A CMOS inverter is built in a process where K n’=100µA/V2


VTn=0.70 V Kp’=42µA/ V2 VTp= - 0.80 V

and a power supply of VDD=3.3V is used.Find the mid point


voltage VM if (W/L)n =10 and (W/L)p=14.

2.) Find the ratio βn/βp needed to obtain an inverter midpoint


voltage of VM =1.3V with a power supply of 3V.Assume that
VTn=0.60 V and VTp= - 0.82 V .What would be the relative device
sizes if Kn’=110uA/V2 and the mobility values are related by
µn=2.2µp?

3.) A inverter uses FETs with βn =2.1mA/ V2 and βp =1,8mA/


V2 .The threshold voltages are given as VTn=0.60 V and VTp=-
0.70 V and the power supply has a value of V DD=5V .The parasitic
FET capacitance at the output node is estimated to be C FET =74fF.

a) Find the midpoint voltage VM?


b) Find the values of Rn and Rp .
c) Calculate the fall and rise times at the output when C L=0.
d) Calculate the fall and rise times when an external load of
value CL =115fF is connected to the output.
e) Plot tr and tf as function of CL .

4.) Find the midpoint voltage for the inverter layout shown in
figure 7.11?

5.) Consider the NOT gate shown in figure 7.11 when an external
load of CL=80fF is connected to the output. Note that the
electrical channel length is L=.8µm.

a) Find the input capacitance of the circuit


b) Find the values of Rn and Rp .
c) Calculate the fall and rise times for the inverter.

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