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Lec 12 Dynamic Logic

The document discusses dynamic logic in VLSI design, highlighting its advantages over static CMOS logic, such as reduced area and lower static and dynamic dissipation. It explains the properties of dynamic gates, including the need for pre-charge and evaluation phases, and addresses challenges like charge sharing and capacitive coupling. The content emphasizes the speed benefits of dynamic logic while noting potential issues like higher power dissipation and sensitivity to crosstalk.

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7 views26 pages

Lec 12 Dynamic Logic

The document discusses dynamic logic in VLSI design, highlighting its advantages over static CMOS logic, such as reduced area and lower static and dynamic dissipation. It explains the properties of dynamic gates, including the need for pre-charge and evaluation phases, and addresses challenges like charge sharing and capacitive coupling. The content emphasizes the speed benefits of dynamic logic while noting potential issues like higher power dissipation and sensitivity to crosstalk.

Uploaded by

kanha dd
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 26

VLSI Design : 2021-22

Lecture 12
Dynamic Logic

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


Static CMOS Logic

F=A+B+C+D
F= {[(A+B)+(C+D)]’}’
F= {(A+B)’.(C+D)’}’

➢Area Large
➢Static Dissipation
➢Dynamic Dissipation
Short Circuit
Switching Loss

2
Static Full Adder

3
Dynamic Logic

CLK Mp

Out ➢Area Less


➢Lesser Static Dissipation
A ➢Lesser Dynamic Dissipation
Short Circuit
B Switching Loss

CLK Me

4
Static vs. Dynamic

In static circuits at every point in time (except when switching)


the output is connected to either GND or VDD via a low
resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices

Dynamic circuits rely on the temporary storage of signal values


on the capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors

5
Dynamic Gate

DG needs periodic sequence of pre-charges and evaluations

6
Properties of Dynamic Gate

➢ Once the output of a dynamic gate is discharged, it cannot be


charged again until the next pre-charge operation.

➢ Inputs to the gate can make at most one transition during


evaluation.

➢ Output can be in the high impedance state during and after


evaluation (PDN off), state is stored on CL

7
Properties of Dynamic Gate
➢ Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary
CMOS)

➢ Full swing outputs (VOL = GND and VOH = VDD)

➢ Non-ratioed - sizing of the devices does not affect the


logic levels
➢ Faster switching speeds
reduced load capacitance due to lower input capacitance
reduced load capacitance due to smaller output loading
reduce logical effort no Isc, so all the current provided by PDN
goes into discharging CL

8
Properties of Dynamic Gate

➢ Overall power dissipation usually higher than static CMOS (


for low input switching activity)
No static current path ever exists between VDD and GND
(including Psc)
Higher transition probabilities
Extra load on Clk

➢ PDN starts to work as soon as the input signals exceed VTn, so


VM, VIH and VIL equal to VTn
Low noise margin (NML)
Needs a precharge/evaluate clock

9
Speed of Dynamic Logic
Main advantages are increased speed and reduced implementation
area
For low input signal no additional switching occurs tpLH = 0!

Pre-charge time should coincide with other system function “Dead


Zone”
o For Microprocessor instruction decode

10
Transition Activity

11
Transition Activity

12
Transition Activity

13
Dynamic Logic
➢ Dynamic Logic Suffers from Charge Sharing Phenomenon

Case1. ΔVout < VTn-Vout



Y VDD.CY = VY C Y + (VDD- VTn)CX
A x CY
(VDD− VTn)CX
Cx ΔVout = -
B=0 CY

CX << C Y

14
Dynamic Logic
➢ Dynamic Logic Suffers from Charge Sharing Phenomenon

Case2. ΔVout > VTn-Vout



Y
A CY VDD.CY = VY C Y + VXCX
x
B=0 Cx VDD.CY = VY C Y + VYCX
VDD.CY = (VDD + ΔVout) (C Y + CX)

VDDCX
ΔVout = -
CY+CX

15
Dynamic Logic

16
Dynamic Logic

Solution to Charge Redistribution

Pre-charge internal nodes using a clock-driven transistor (at the cost of


increased area and power)

17
Dynamic Logic

Capacitive Coupling

The high impedance of the output node makes the circuit very sensitive to crosstalk
effects. A wire routed over a dynamic node may couple capacitively and destroy the
state of the floating node.

18
Dynamic Logic
Backgate (or output-to-input) coupling

19
Dynamic Logic

Solution to Charge Redistribution Keeper PMOS used to


restore high state

20
Dynamic Logic

Contention

21
Dynamic Logic

[7] M.E.S Elraba, M.H Anis, M.I Elmasry, “A contention-free domino logic for scaled down
CMOS technologies with ultra low threshold voltages,” Proc. of IEEE International
Symposium on Circuits and Systems pp. 748 - 751, May 2000.

22
Dynamic Logic

Clock-Feedthrough

23
Dynamic Logic

24
Dynamic Logic

➢ Cascading Dynamic Gates

25
Thank you

3/25/2022 26

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

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