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Lec-8 - Dynamic Logic

This document discusses dynamic logic. It begins by comparing static CMOS logic and dynamic logic. Dynamic logic uses less area and has less static and dynamic dissipation than static CMOS, but relies on temporary storage of signals and requires a pre-charge and evaluate clock. Dynamic gates suffer from problems like charge sharing and charge redistribution but these can be addressed using techniques like keeper transistors. The document outlines various properties of dynamic logic and issues that can arise like contention, clock feedthrough, and cascading dynamic gates.

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13 views28 pages

Lec-8 - Dynamic Logic

This document discusses dynamic logic. It begins by comparing static CMOS logic and dynamic logic. Dynamic logic uses less area and has less static and dynamic dissipation than static CMOS, but relies on temporary storage of signals and requires a pre-charge and evaluate clock. Dynamic gates suffer from problems like charge sharing and charge redistribution but these can be addressed using techniques like keeper transistors. The document outlines various properties of dynamic logic and issues that can arise like contention, clock feedthrough, and cascading dynamic gates.

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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 28

VLSI Design : 2022-23

Lecture 8
Dynamic Logic

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION


Static CMOS Logic

F=A+B+C+D
F= {[(A+B)+(C+D)]’}’
F= {(A+B)’.(C+D)’}’

➢Area Large
➢Static Dissipation
➢Dynamic Dissipation
Short Circuit
Switching Loss

2
Static Full Adder

3
CMOS 28T Mirror Adder

𝐶𝑎𝑟𝑟𝑦 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐴 = 𝐴𝐵 + 𝐶 𝐴 + 𝐵

𝑃𝑢𝑙𝑙 − 𝐷𝑜𝑤𝑛 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑓𝑜𝑟 𝐶𝑎𝑟𝑟𝑦 𝐵𝑎𝑟 = 𝐴𝐵 + 𝐶 𝐴 + 𝐵

𝑃𝑢𝑙𝑙 − 𝑈𝑃 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑓𝑜𝑟 𝐶𝑎𝑟𝑟𝑦 𝐵𝑎𝑟 = 𝐴′ 𝐵′ + 𝐵′ 𝐶 ′ + 𝐶 ′ 𝐴′


= 𝐴′ 𝐵′ + 𝐶′(𝐴′ + 𝐵′ )

3/18/2023 4
4
CMOS 28T Mirror Adder

12 12 12

12 12

6 6

6 6 6

Carry Delay = 2 Gate Delay and Sum = 3 Gate Delays


3/18/2023 5
5
Dynamic Logic

CLK Mp

Out ➢Area Less


➢Lesser Static Dissipation
A ➢Lesser Dynamic Dissipation
Short Circuit
B Switching Loss

CLK Me

6
Static vs. Dynamic

In static circuits at every point in time (except when switching)


the output is connected to either GND or VDD via a low
resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices

Dynamic circuits rely on the temporary storage of signal values


on the capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors

7
Dynamic Gate

DG needs periodic sequence of pre-charges and evaluations

8
Properties of Dynamic Gate

➢ Once the output of a dynamic gate is discharged, it cannot be


charged again until the next pre-charge operation.

➢ Inputs to the gate can make at most one transition during


evaluation.

➢ Output can be in the high impedance state during and after


evaluation (PDN off), state is stored on CL

9
Properties of Dynamic Gate
➢ Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary
CMOS)

➢ Full swing outputs (VOL = GND and VOH = VDD)

➢ Non-ratioed - sizing of the devices does not affect the


logic levels
➢ Faster switching speeds
Reduced load capacitance due to lower input capacitance
Reduced load capacitance due to smaller output loading
Reduced logical effort
No Isc so all the current provided by PDN goes into discharging CL

10
Properties of Dynamic Gate

➢ Overall power dissipation usually higher than static CMOS (


for low input switching activity)
No static current path ever exists between VDD and GND
(including Psc)
Higher transition probabilities
Extra load on Clk

➢ PDN starts to work as soon as the input signals exceed VTn, so


VM, VIH and VIL equal to VTn
Low noise margin (NML)
Needs a pre-charge / evaluate clock

11
Speed of Dynamic Logic
Main advantages are increased speed and reduced implementation
area
For low input signal no additional switching occurs tpLH = 0!

Pre-charge time should coincide with other system function “Dead


Zone”
o For Microprocessor instruction decode

12
Transition Activity

13
Transition Activity

14
Transition Activity

15
Dynamic Logic
➢ Dynamic Logic Suffers from Charge Sharing Phenomenon

Case1. ΔVout < VTn-Vout



Y VDD.CY = VY C Y + (VDD- VTn)CX
A x CY
(VDD− VTn)CX
Cx ΔVout = -
B=0 CY

CX << C Y

V= Q/C

16
Dynamic Logic
➢ Dynamic Logic Suffers from Charge Sharing Phenomenon

Case2. ΔVout > VTn-Vout



Y
A CY VDD.CY = VY C Y + VXCX
x
B=0 Cx VDD.CY = VY C Y + VYCX
VDD.CY = (VDD + ΔVout) (C Y + CX)

VDDCX
ΔVout = -
CY+CX

17
Dynamic Logic

18
Dynamic Logic

Solution to Charge Redistribution

Pre-charge internal nodes using a clock-driven transistor (at the cost of


increased area and power)

19
Dynamic Logic

Capacitive Coupling

The high impedance of the output node makes the circuit very sensitive to crosstalk
effects. A wire routed over a dynamic node may couple capacitively and destroy the
state of the floating node.

20
Dynamic Logic
Backgate (or output-to-input) coupling

21
Dynamic Logic

Solution to Charge Redistribution Keeper PMOS used to


restore high state

22
Dynamic Logic

Contention

23
Dynamic Logic

[7] M.E.S Elraba, M.H Anis, M.I Elmasry, “A contention-free domino logic for scaled down
CMOS technologies with ultra low threshold voltages,” Proc. of IEEE International
Symposium on Circuits and Systems pp. 748 - 751, May 2000.

24
Dynamic Logic

Clock-Feedthrough

25
Dynamic Logic

26
Dynamic Logic

➢ Cascading Dynamic Gates

27
Thank you

3/18/2023 28

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

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