Dynamic CMOS logic NMOS Evaluate inputs | network cK Precharge = CLK O01 Two-phase operation: precharge & evaluate O This can fully eliminate static power dissipation © It is designed to avoid the static power dissipation with the addition of a clock input, it uses a sequence of precharge and conditional evaluation phases ‘* In one phase of the clock, we'll precharge the gate to either 0 or 1 In another phase, we'll evaluate whether the gate’s output should stay at the precharged value or change. evaluate ckk=1 ik I clk =0 precharge iccummsowinetesinneen Ey studocu Downloaded by bharatha babu (kbharathababudgmail.com)Dynamic logic recharge” ge switch As _|l/K—s cLK —+——|[+___ “evaluate” switch ‘* Pullup time is improved by active switch * Pull down time is increased by ground switch O To eliminate the static power dissipation of pseudo-NMOS logic & Analternative technique is to use dynamic precharging called dynamic logic as shown below np NMOS network y © Normally, during the time the output is being precharged, the NMOS network should not be conducting O This is usually not possible inputs Downloaded by bharatha babu (kbharathababudgmal.com)Iny Ing Ing (@) n-type network Figure 6.62 Basic concepts of a dynamic gate Working of dynamic cmos logic * When CLK is low evaluate n transistor (Me) is off and precharge p transistor (Mp) is on output node is precharged to VDD, other nodes may precharge to VDD-Vin, depending on values of inputs © When CLK goes high evaluate n transistor is on and precharge p transistor is off output node may be discharged * the output is conditionally discharged to GND, based on the input values and the pull-down Topology otherwise output node stays Charged high. ‘Inputs must be stable before CLK goes high * Because once output has been discharged it won’t go high again until next cycle * The inputs to the gate can therefore make at most one transition during evaluation. The output can be in the high-impedance state during the evaluation period if the pull-down network is tuned off. iccummsowinetesinneen Ey studocu Downloaded by bharatha babu (kbharathababudgmail.com)‘+ Ifthe PDN is tumed off, the precharged value remains stored on the output capacitance CL, which is a combination of junction capacitances, the wiring capacitance, and the input capacitance of the fan-out gates, Example circuit * During the precharge phase (CLK=0), the output is precharged to VDD regardless of the input values since the evaluation device is tuned off. During evaluation (CLK=1), a conducting path is created, * between Out and GND if (and only if) A:B+C is TRUE. Otherwise, the output remains at the precharged state of VDD. (©) Example Examples of Dynamic Logic 0 Two examples c4 ZRBC Downloaded by bharatha babu (kbharathababu@2amalcom)»— |e 4 Ke 24 iB COrH ont z= HoH oro Properties of dynamic logic gate * The logic function is implemented by the NMOS pull-down network. ‘© The construction of the PDN proceeds just as it does for static CMOS © The number of transistors (for complex gates) is substantially lower than in the static case: N +2 versus 2N. * Itisnon-ratioed. The sizing of the PMOS precharge device is not important for realizing proper functionality of the gate. ‘© The size of the precharge device can be made large to improve the low-to- high transition © There is a trade-off with power di ipation since a larger precharge device directly increases clock-power dissipation, + It only consumes dynamic power. Ideally, no static current path ever exists between VDD and GND. The overall power di ipation, can be significantly higher compared to a static logic gate. iccummsowinetesinneen Ey studocu Downloaded by bharatha babu (kbharathababudgmail.com)‘The logic gates have faster switched speeds. There are two main reasons for this. ‘The first reason is due to the reduced load capacitance attributed to the lower number of transistors per gate and the single-transistor load per fan-in. ‘* Second, the dynamic gate does not have short circuit current, and all the current provided by the pull-down devices goes towards discharging the load capacitance © The low and high output levels VOL and VOH are easily identified as GND and VDD and are not dependent upon the transistor sizes. ‘* Noise margins and switching thresholds have been defined as static quantities that are not a function of time. Issues in Dynamic Design © Charge sharing © Capacitive coupling * Charge leakage * Simple single phase dynamic logic cannot be cascaded Problems of Dynamic Logic C0 Two major problems of dynamic logic ™ Charge sharing ™ Simple single-phase dynamic logic can not be cascaded 1 Charge sharing Co tm tee, ce. te, re) c ToT] “reare charge sharing model E.g,,f C, =C, =0.5C then output voltage is Downloaded by bharatha babu (kbharathababu@2amallcom)