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Final Lect 2

The document discusses sequential circuit design focusing on counters, which are devices used for counting in digital circuits. It categorizes counters into asynchronous and synchronous types, detailing their operations, designs, and specific examples such as MOD-10 and MOD-12 counters. Additionally, it covers the design of irregular sequence counters and state machines, providing a structured approach to developing these circuits.

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13 views32 pages

Final Lect 2

The document discusses sequential circuit design focusing on counters, which are devices used for counting in digital circuits. It categorizes counters into asynchronous and synchronous types, detailing their operations, designs, and specific examples such as MOD-10 and MOD-12 counters. Additionally, it covers the design of irregular sequence counters and state machines, providing a structured approach to developing these circuits.

Uploaded by

magentamadlen
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture -2

Sequential Circuit Design: Counters


Prepared By: Asif Mahfuz
Asynchronous Counter
COUNTERS: Counters in digital circuit are devices used for counting. These are sequential
circuits made of flip-flops. There are two broad categories of counters, namely,
Asynchronous Counters are counters where the flip-flops do not have a common clock and
so they do not change states at the same time.
Synchronous Counters are counters where the flip-flops have a common clock and so the
flip-flop changes its states at the same time.

The clock is not


common The clock is common
Asynchronous Counter
• Flip-Flops are not connected to a common clock.
• Flip-Flops do not change their state at the same time.
• JK flip-flops are used in toggle mode of operation.

Common Asynchronous Counter


• Asynchronous Binary Counters
➢ 2- Bit Binary Counters
➢ 3- Bit Binary Counters
➢ 4- Bit Binary Counters
• Asynchronous Decade Counter ( MOD-10)
• Asynchronous Modulus Twelve Counter
2-Bit Binary Asynchronous Counter

+ve edge-triggered J-K Flip-Flop

Toggle Toggle
Toggle
Toggle

Toggle Toggle
3-Bit Binary Asynchronous Counter
4-Bit Binary Asynchronous Counter
MOD Counters
• A counter with N flip-flops can count to 2N sequences.
• The modulus of a counter in number of unique sequence that a counter can count
through.
• The MOD counters do not complete the entire count sequence.
• These type of sequence is called truncated sequence.
• An example of such counter can be MOD-11 counter.
• A MOD-11 counter has 4 flip-flops (as we require 4-bits to count up to 11)
• With 4 flip-flops the complete count sequence is 16 (0 to 15).
• However, a MOD-11 counter will have only 11 sequences (0 to 10).
• Thus we need to figure out a way to reset the flip-flop when the counter reaches the 12th
sequence (no. 11).
• This is where the asynchronous clear input becomes very handy.
• So we can decode the 12th state to reset the counter.
Asynchronous Decade Counter (MOD-10)
• The most popular MOD counter is the Decade Counter.
• Counters with 10 sequences are called Decade Counters.
• It can count 10 sequence that is 0 to 9.
• Thus it is also called a BCD counter. BCD = Binary Coded Decimal
• It has a wide range of application from displays to digital
watches.
• The counter counts from 0000 to 1001.
• Then when counter reach 1010 the counter resets.
• So the state 1010 is decoded to reset the counter.

Since we do not want the states after 1001, at


1010 we force clear the counter and restart
counting from 0000.
Asynchronous Decade Counter (MOD-10)

To decode 1010, we can


only use the outputs Q3
and Q1. NAND of Q1 and Q3
produces a 0 when both
Q1 and Q3 are 1. And the
output of the NAND gate is
used to clear the flip-flops

NAND is used instead of AND since


CLR is active-low

As the counter changes its state


from 1001 to 1010(for fraction of
seconds), the counter is reset by
the help of clear. This produces
the glitch
Asynchronous MOD-12 Counter

At state 0000 and 1100 NAND of Q2 and Q3 at 1100


Q0 and Q1 are already 0 state produces a 0 which
so need to clear these clears FF2 and FF3.
two flip-flops.
Synchronous Counter
• Flip-Flops are connected to a common clock.
• Flip-Flops change their state at the same time.
• JK flip-flops are used.
• The design is complex compared to asynchronous counters.

Common Synchronous Counter


• Synchronous Binary Counters
➢ 2- Bit Binary Counter
➢ 3- Bit Binary Counter
➢ 4- Bit Binary Counter
• Synchronous BCD Decade Counters
• Up/ Down Synchronous Counters
• Irregular Sequence Counters
2-Bit Synchronous Counter
• 2-Bit Binary Counter count from 0 up to 3 and then resets.
• Unlike asynchronous counter we need find the inputs to the
flip-flop.
• The first bit alternates at every clock
• So the first flip-flop can be used in toggle mode.
• But for the second bit we need to find the pattern that
toggles the bit.
2-Bit Synchronous Counter

Toggle Toggle Toggle


Toggle
J1 = 1, K1 = 1 J1 = 1, K1 = 1
J1 = 0, K1 = 0 J1 = 0, K1 = 0

Toggle Toggle
3-Bit Synchronous Counter
4-Bit Synchronous Counter
Synchronous BCD Decade Counter
Why do we need
𝑸𝟑 ??

Why do we need
Synchronous BCD Decade Counter
Up-Down Synchronous Counter
• An up/down counter is one that is capable of progressing in either direction through a
certain sequence.
• It is also called a bi-directional counter.
• In general most up/down can be reversed at any point in their sequence
Up-Down Synchronous Counter
Up-Down Synchronous Counter
Irregular Sequence Counter
To design an irregular sequence counter we need to first understand the concept of state
machines. A state machine is a sequential circuit having a finite number of states occurring
in prescribed order. There are generally two types of state machines, namely, Moore State
Machine and Mealy State Machines.

Moore Machine Mealy Machine


• State Machines have a finite number of state and they go about it in a prescribed manner.
• The order of sequence is described with the help of a state diagram.
• A state diagram is a diagram which shows the progression of states through which the
counter advances when it is clocked.
Irregular Sequence Counter (Gray Code Counter) Design
Step1: Develop a state Diagram
Step2: Develop a Next-state table.
Step3: Create a flip-flop transition table.
Step4: Use Karnaugh-map to derive the logic requirements.
Step5: Implement a counter to produce the specific sequence of states.

STEP 1 STEP 2
Irregular Sequence Counter (Gray Code Counter) Design

STEP 3

Once the table is populated, considering present state as output K-Map for J and K for the
three flip-flops are filled and the logic requirements are found.
Irregular Sequence Counter (Gray Code Counter) Design

STEP 4
Irregular Sequence Counter (Gray Code Counter) Design

3-Bit Gray Code Counter Circuit


STEP 5
Irregular Sequence Counter Design
• Design a counter with the sequence 1,2,5 and 7.
Irregular Sequence Counter Design
Irregular Sequence Counter Design

FROM THE K-MAP

The implementation of the counter for the given states


Irregular Sequence Counter Design

State Diagram
Irregular Sequence Counter Design
Irregular Sequence Counter Design
Logic Requirements for the inputs J and K:

Please draw the circuit for the counter on your own!!!!!!!!!!


References
1. Thomas L. Floyd, “Digital Fundamentals” 11th edition, Prentice Hall – Pearson Education.

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