Q1 a.What is the meaning of ALE signal?

ANS. ALE – It is an Address Latch Enable signal. It goes high during first T state of a machine
cycle and enables the lower 8-bits of the address, if its value is 1 otherwise data bus is activated.
Q1 (b) The content of the accumulator are 93H and contents of register C are B7H. Add
both contents and determine the sign, carry and zero flag status.
ANS. CF=1, SF=0 and ZF=0
Q1 (c) Define the term RISC and CISC.
ANS. In RISC, the instruction set is reduced, and most of these instructions are very primitive,
while in CISC, the instruction set is very large that can be used for complex operations.

• RISC computer’s execution time is very less, whereas CISC computer’s execution time
is very high.
• RISC code expansion may create a problem, while CISC code expansion is not a
problem.
• In RISC, the decoding of instructions is simple, whereas, in CISC, the decoding of
instructions is complex.
• RISC doesn’t require external memory for calculations, but CISC requires external
memory for calculations.
• RISC has multiple registers sets present, while CISC has only a single register set.

Q1 (d) What are the advantage of using memory segmentation?

ANS. Segmentation provides a powerful memory management mechanism. It allows

programmers to partition their programs into modules that operate independently of one
another. Segments allow two processes to easily share data.

Q1 (e) What is BSR mode?

ANS. Bit set reset (BSR) mode – This mode is used to set or reset the bits of port C only, and
selected when the most significant bit (D7) in the control register is 0.

Q1 (f) What do you mean by RS-232C?

ANS.RS-232C is one of the earlier versions of the long-established standard RS-232, which
defines a physical interface for relatively low-speed serial data communication between
computers and related devices. The RS in RS-232C stands for "Recommended Standard," and
the C refers to the version.
 Q1 (g) Show the status of CY, AC and P flag after addition of 56H & 95H in the following
instruction.
MVI A, 56H
MVI B, 95H
ADD B

ANS. CY flag=0
AC flag=0
P flag=1

Q1 (h) What is the difference between microprocessor and microcontroller?

ANS.A microprocessor is a processor where the memory and I/O component are connected
externally. A microcontroller is a controlling device wherein the memory and I/O output
component are present internally. The circuit is complex due to external connection.
Microcontrollers are present on chip memory

Q1 (i)What do you mean by ARM?

ANS. ARM processors are a family of central processing units (CPUs) based on a reduced
instruction set computer (RISC) architecture. ARM stands for Advanced RISC Machine.

Q1 (j) What is PSW?

ANS.PSW (program status word) register The program status word (PSW) register is an 8-bit
register. It is also referred to as the flag register.

Q2(a) Draw the internal architecture of 8085. Also explain flag register of 8085.

ANS.8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor

designed by Intel in 1977 using NMOS technology.
It has the following configuration −
• 8-bit data bus
• 16-bit address bus, which can address upto 64KB
• A 16-bit program counter
• A 16-bit stack pointer
• Six 8-bit registers arranged in pairs: BC, DE, HL
• Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.
8085 Microprocessor – Functional Units
8085 consists of the following functional units −
Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It
is connected to internal data bus & ALU.
Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction,
AND, OR, etc. on 8-bit data.
General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed,
so that the program counter points to the memory address of the next instruction that is going
to be executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
These are the set of 5 flip-flops −
• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)
Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY
Instruction register and decoder
It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the Instruction
register.
Timing and control unit
It provides timing and control signal to the microprocessor to perform operations. Following
are the timing and control signals, which control external and internal circuits −
 • Control Signals: READY, RD’, WR’, ALE
• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT
Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is
executing a main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request is completed,
the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.
Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address buffer
and address-data buffer to communicate with the CPU. The memory and I/O chips are
connected to these buses; the CPU can exchange the desired data with the memory and I/O
chips.
Address bus and data bus
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location
to where it should be stored and it is unidirectional. It is used to transfer the data & Address
I/O devices.
8085 Architecture
Q2 (b) Draw the pin diagram of 8086 and also discuss about BIU and EU.

ANS. Pin Diagram and Description of 8086 Microprocessor

8086 is a 16-bit microprocessor and was created by Intel in 1978. Like the pin configuration
of 8085 microprocessor, the 8086 microprocessor also contains 40 pins dual in line.However,
unlike the 8085 microprocessor, an 8086 to have better performance, operates in 2 modes that
are minimum and maximum mode.The minimum mode is a single processor configuration
while the maximum mode is a multiple processor configuration. Due to this reason, in the 40
pin IC of 8086 microprocessor, 8 pins i.e., pin numbered from 24 to 32 are assigned different
configurations separately according to the two modes.
Pin Diagram 8086 Microprocessor

An 8086 microprocessor is also a 40 pin IC but has few separate pin configuration for minimum
and maximum mode.

The figure below represents the pin diagram of 8086 microprocessor:

Here, from the above figure it is clear that from pin number 24 to 32, we have shown the
different configuration for minimum and maximum mode. However, excluding these 8 pins,
the rest 32 pins are the same for both minimum as well as maximum mode.

Pin description of 8086 Microprocessor

VCC – Pin number 40 – At this pin, the external power supply of + 5V is provided to the
processor.
VSS – Pin number 1 and 20 – These two pins acts as the ground. This pin directs the extra
current of the microprocessor to ground.
AD0 – AD15 – Pin number 2 to 16 and 39 – These are the multiplexed address and data bus.
We know that the 8086 microprocessor has 20-bit address bus and 16-bit data bus. So, the 16
lines of the address and data bus are multiplexed together so as to reduce the number of lines
inside the IC.
We are aware of the fact that at a time either address or data will be transmitted by the bus. So,
at a particular time only either the address or the data bus will be enabled from the multiplexed
buses.

A16/S3, A17/S4, A18/S5 and A19S6 – Pin number 35 to 38 – Out of 20 address bits, 4 are present
in the multiplexed form with the status signals. In the case of memory operations, these pins
act as an address bus and contain the memory address of any particular instruction or data.
However, from I/O operations these pins are low that shows the status of the processor.

Basically, the signal at S3 and S4 show that which segment is currently accessed by the
microprocessor among the four segments present in it.
The table below will show the encoding of S3 and S4:

Also, S5, when enabled, shows the presence of an interrupts in the microprocessor. So,
basically, it serves as an interrupt flag.
The signal at S6 shows the status of the bus master for the current operation. More simply we
can say, whether the 8086 is the bus master or any other proficient device is acting as the bus
master.
When 0 is present as the signal at this pin then it indicates the 8086 is holding the access of the
bus otherwise it is high i.e., 1.

BHE’ / S7 – Pin number 34 – BHE is an acronym for Bus High Enable. The combination of
the BHE signal and S7 status informs about the existence of the data on the bus. Also, different
combinations show whether the bus is containing overall 16 bit, upper byte or lower byte of
the data.
The table below represents the status for the signal at this pin:
MN/MX’ – Pin number 33 –The status at this particular pin shows whether the processor is
operating in the minimum mode or maximum mode.
A signal 0 at this pin informs that the 8086 is operating in maximum mode i.e., multiple
processors. While signal 1 shows the operation under minimum mode i.e., single processor.

RD’ – Pin number 32 – An active low signal at this pin shows that the microprocessor is
performing read operation with either memory or I/O devices.
CLK – Pin number 19 – A signal at this pin provides the timing to the internal operations that
are being executed inside the microprocessor.
NMI – Pin number 17 – NMI is Non-maskable interrupt. These are basically uncontrollable
interrupts generated inside the processor. When an NMI occurs, then an interrupt service
routine is generated by the interrupt vector table.
TEST – Pin number 23 – This pin basically shows the wait instruction. Whenever a low signal
at this pin occurs then the processing inside the processor continues. As against, in case of the
high signal, the processor has to wait for the disabling of this pin.
INTR – Pin number 18 – INTR stands for an interrupt request. The processor after each clock
cycle samples the INTR and if the signal at this pin is found to be high then the processor
controls that interrupt internally.
READY – Pin number 22 – This signal is used by the peripherals and memory devices in
order to show the readiness for the next operation.
RESET – Pin number 21 – Whenever this pin is enabled then it resets the processor and other
devices connected to the system by immediately terminating the recent task.
Pins in Minimum mode

INTA’ – Pin number 24 – It is an interrupt acknowledge pin. Whenever an INTR signal is

generated, then the microprocessor generates INTA signal, as a response to that interrupt.
ALE – Pin number 25 – ALE is an abbreviation for address latch enable. Whenever an address
is present in the multiplexed address and data bus, then the microprocessor enables this pin.
This is done to inform the peripherals and memory devices about fetching of the d ata or
instruction at that memory location.

DEN’ – Pin number 26 – DEN is used for data enable. This is an active low pin that means
whenever a 0 is present at this pin then the transceiver gets enabled and it separates the data
from the multiplexed address and data bus.
DT/R’ – Pin number 27 – This pin is used to show whether the data is getting transmitted or
is received. A high signal at this pin provides the information regarding the transmission of
data. While a low indicates reception of data.
M/IO’ – Pin number 28 – This pin indicates whether the processor is performing an operation
with memory or I/O devices. Whenever a high is present at this pin then it shows the operation
is carried out through the memory. While a low signal shows operation through I/O devices.
WR’ – Pin number 29 – An active low signal at this pin indicates that the processor is
performing write operation from either memory or I/O devices.
HOLD – Pin number 31 – When an external device enables this pin then the processor stops
accessing the buses immediately after the recent task gets over.
HLDA – Pin number 30 – This pin is used as a response pin for the hold request. Once request
for accessing the buses is produced by an external entity. Then the microprocessor
acknowledges the device that its request will be considered once it gets over by the current
operation.
Pins in Maximum mode

S0‘, S1‘ and S2‘ – Pin number 26 to 28 – These are basically 3 status pins and are active low.
This means that if the status at all the 3 pins is 0 then it shows that multiple interrupts are to be
handled in maximum mode.
The table below is representing the status of the processor in different combinations:

QS0 and QS1 – Pin number 24 and 25 – These two pins indicate the status of the 6-byte pre-
fetch queue present in the architecture of 8086.
LOCK’ – Pin number 29 –This pin is involved in maximum mode operation. So, basically,
when a single processor is accessing the buses and peripherals then it locks the resources being
used by it. So, that no other entity can access it until the recent processor frees it.
RQ’/ GT0‘ and RQ’/ GT1‘ – Pin number 30 and 31 – Due to the involvement of multiple
processors, these pins indicate the request and grant permission for accessing the buses,
memory and peripherals.

Q2 (c) Explain 8237 DMA controller in detail.

ANS. 8237 is a high-performance programmable DMA controller. Some of the important

features of 8237 DMA controllers are mentioned below:

Features of 8237 DMA Controller:

• It provides various modes of Direct memory access (DMA).

• It provides on-chip four independent DMA channels. The number of channels
can be increased by cascading DMA controller chips.
• Each channel can be used in auto initialization mode.
• It can transfer data between two memory clocks in DMA mode i.e. memory to
memory transfer.
• In memory-to-memory transfer, a single word can be written into all locations
of memory blocks.
• The address of memory is either incremented or decremented after each DM
cycle depending upon the mode.
• The clock frequency is 3 MHz (8237 DMA C0ntroller) or 5 MHz (8237-2 DMA
Controller).
• The data transfer rate is very high i.e. 1.6 Mbytes/second for 8237-2 at 5 MHz.
• Directly expandable to any number of channels. It doesn’t require any additional
chip for cascading. There are no limitations in cascading.
• The DMA can be requested by setting an appropriate bit for the request register.
• It provides compressed timings to improve the throughput of the system. It can
compress the transfer time to two cycles (2s).
The pin configuration of the 8237 DMA controller is shown in the below figure
Symbol Description

This is the clock input line ignored in slave mode. In master mode, this signal control all int
CLK
and external DMA operations. The data transfer rate depends upon the frequency of this sign

In slave mode, this signal is generated by the address decoder to select the 8237 chi
CS
communication between the CPU and 8237. In master mode, this signal is ignored.

It is an asynchronous input line. This signal clears the command, status, request, and temp
Reset
register and forces 8237 into slave mode.

READY In master mode, this signal is used to add wait states into the DMA cycle.

It is a hold request output line. It is connected to hold the input of the CPU. it is used to re
HRQ
control of the system bus.
Symbol Description

It is a hold acknowledge input line. This signal is generated by the CPU. In response to this s
HLDA
the 8237 gains control of the system bus and enters master mode.

It is an active low bi-directional tristate line. In slave mode, it acts as an input line and is us
IOR read the contents of the 8237 register. In master mode, it acts as an output line. This sign
generated during the DMA cycle to read data from the I/O device.

It is an active low bi-directional tristate line. In slave mode, it acts as an input line and is us
IOW write the contents to the 8237 register. In master mode, it acts as an output line. This sign
generated during the DMA read cycle to write data into the I/O device.

These are bi-directional, address lines. In slave mode, these lines act as input lines, used to s
A0 – A3 one of the registers of 8237. In master mode, the 8237 provides lower bits of memory addre
these lines.

These are tristate address output lines. These lines are tri-stated in slave mode. In master mod
A4 – A7
827 transfers bits of memory addressed on these lines.

It is an active low tristate output line. it is tri-stated in slave mode. In master mode, this sign
MEMR generated during the DMA read cycle or during memory to memory transfer cycle to rea
contents of source memory.

It is an active low tristate output line. it is tri-stated in slave mode. In master mode, this sign
MEMW activated during the DMA write or during the memory-to-memory transfer cycle to write dat
destination memory.

These are bi-directional tristate buffered data lines. In slave mode, these lines are used to tra
DB0 – DB7 data between the CPU and 8237 registers. In master mode, these lines act as address output
The 8237 places a higher byte of address on these lines during DMA cycles.

These are asynchronous DMA channel request lines used by the peripheral. The polarity of
DREQ0 –
signal is programmable i.e. these lines can be used as either active high or active low input. D
DREQ3
must be maintained until the corresponding DACK is activated.

DACK0 – These are DMA acknowledge output lines. The polarity of each line is programmable. The s
DACK3 indicates that the requesting peripheral has been granted for the DMA cycle.
 Symbol Description

End of Process: It is an active low bi-directional signal This line is also used to terminate the D
EOP cycle. The DMA cycle can be terminated by pulling‾EOP input low. The 8237 also generat
EOP pulse, when the terminal count for any channel is reached.

The block diagram of the 8237 DMA controller is shown in the below figure. It consists of
logic blocks and internal registers.

Types of Registers in 8237 DMA Controller

There are 12 types of registers in 8237 DMA Controller. It contains 344 bits of internal memory
in the form of registers.

1. Current Address Register

• Each channel has a 16-bit current address register.

• This register holds the address of the memory location to be accessed during the
current DMA cycle. The address stored in this register is automatically
incremented or decremented after each transfer.
• It is a read-and-write register.
• It is divided into two parts: lower byte and higher byte.
• In auto initialization mode, it is initialized automatically with the original
address after EOP signal.
2. Current Word Register

• Each channel has a 16-bit current word count register.

• The original value stored in this register indicates the number of bytes to be
transferred.
• The word count is decremented after each transfer. The current count indicates
the number of pending transfers.
 • When the count value in the register goes to zero, a TC will be generated. it is a
read-and-write register. It is also divided into two parts: lower byte and higher
byte.
• In auto initialization mode, this register is initialized automatically with the
original count value after EOP signal.
3. Base Address Register

• Each channel has a 16-bit base address register.

• It is a write-only register.
• It holds the original value of the address during all MDA transfers i.e. the
contents of this register are not updated during DMA transf er.
• When EOP is activated, the 8237 transfers contents of base address registers
into the current address register in auto initialization mode.
• This register is written along with the current address register during
initialization. The format is the same as the current address register.
4. Base Count Register

•
Each channel has a 16-bit base word count register.
•
It is a write-only register.
•
It holds the original count value during all DMA cycle i.e. the content of this
register are not updated during DMA transfers.
• When EOP is activated, the 8237 transfers contents of this register into the
current word register in auto initialization mode.
• This register is written along with the current address register during
initialization. The format is the same as the current word register.
5. Command Register

• It is an 8-bit control register. It is a write-only register.

• This register is cleared by a reset signal. It is used to initialize operation modes
of 8237.
• The format of the command register is shown in the below figure.

6. Mode Register

• It is an 8-bit write-only register.

• It is used to set the operation modes of the 8237 DMA controller.
• Each channel has a 6-bit mode register.
• All registers are cleared by the reset signal. The format of the mode register is
shown below.

7. Request Register
 • It is an 8-bit write-only register.
• It is used to request DMA through software. Each channel has a request bit
associated with it in the 4-bit request register.
• Each register bit is set or reset separately under software control The request is
automatically cleared after TC. It is also cleared by external EOC signal.
• This register is cleared by a reset signal.
• In memory-to-memory transfer, the software request for channel 0 should be
set. The format f the request register is shown in the figure below.

8. Mask Register

• It is an 8-bit write-only register.

• It is used to mask out the channel DMA request.
• In normal mode, the mask bit is set automatically after TC. It is not affected by
auto initialization mode.
• The reset signal sets the mask bit of all channels i.e. it disables all channels.
9. Status Register

•It is an 8-bit read-only register.

•It indicates which channels have reached a terminal count and which channels
have pending DMA requests.
• Bits 0-3 are set every time a TC is reached by that channel or an external EOP
signal is applied.
• These bits are cleared automatically on reading the status register and upo n reset
signal.
• Bits 4-7 are set whenever their corresponding channel is requesting service.
10. Temporary Register

• This register is used to hold data during memory-to-memory transfer.

• It is an 8-bit read-only register.
• The microprocessor can read the last byte of memory to memory transfer.
• It is cleared by a reset signal.
11. Clear First/Last FLip-Flop

• This command is used to reset the internal first/last flip-flop.

• After issuing this command, the microprocessor can access the lower byte of
any 16-bit register. The F/L flip-flop is toggled after each read or write 16-bit
register.
12. Master Clear

• It is a software reset command.

• It clears command, status, request, temporary register, and F/L flip-flop.
• It sets the mask register and forces the 8237 DMA controller into slave mode
13. Software Commands

•These are additional special write-only software commands.

•These commands do not require a specific data pattern. i.e. writing only data
corresponding address enables such commands.
Software Command Codes
DMA Data Transfer Modes

The 8237 DMA controller can be operated in four DMA modes.

Sr. No. DMA Data Transfer Modes

1. Single Transfer Mode

2. Burts or Block Transfer Mode

3. Demand Transfer Mode

4. Cascade Mode

Operating Modes of 8237 DMA Controller

Q2 (d) State the features of 8051 and also draw the block diagram of microcontroller.
ANS. Block Diagram of Microcontroller 8051

CPU – The CPU (Central Processing Unit) comprising of ALU (Arithmetic and Logic Units)
and Control units
ALU - Arithmetic and Logic Unit performing the arithmetic and logical operations. These
operations are multiplication, addition, subtraction, logical AND,OR etc. To do these
operations one operand must be in Accumulator, and another may in B register or in general
purpose register. The ALU operation results are mostly placed in A register. Some results are
placed in B register too.
OSC - Oscillator provides clock for controller operation .Crystal oscillator is used for
providing perfect clock and stability. So this microcontroller uses crystal oscillator. For this
purpose, the crystals linked to the pins are used.
INTERRUPT CONTROLLER
Microcontroller operation needs some interrupts. Here mainly five interrupts are used. The
controller controls the operation interrupts. ie some interrupts may be allowed, some others are
disabled and priority assigned and changed. The five interrupts are:
BUS CONTROL
For both Address and data, lower byte address buses are used. The BUS control controls the
BUS usage. There are 3 control signals: PSEN , EA, and ALE. The signals like Program Store
Enable (PSEN), Address Latch Enable (ALE) and External Access (EA), are used for external
memory interfacing.
ON CHIP RAM
The 8051 has 4 kilobyte of inbuilt ROM. It is otherwise called program memory. Usually
program-code is stored in ROM. To store program into ROM, programmer is needed. If more
area is required in ROM, an external ROM may be connected. Maximum of 64kb ROM
memory can be used.
ON CHIP ROM
The 8051 has an inbuilt of 128 byte RAM, some version have 256 byte and are used as data
memory. If the system needs more memory, external RAM may be connected up to 64kb.In
128 byte RAM chip, 00h to 71Fh are the address range .In this range ,00H to 1FH are the
general purpose registers . 20H to 2F are the bit Addressable area and rest of this is byte
addressable .This is used as general purpose scratch pad. In 256 byte RAM chip, another 128
bytes are used for Special Function Registers.
I/O PORTS
There are four IO ports in 8051.These are named as P0, P1, P2, P3.All are bidirectional. Each
port have its address, output driver, latch and input buffer. Each port is output by default.

SERIAL PORT
TXD and RXD are utilised for serial port. Each pin has separate buffer registers na med as
SBUF.
TIMER/COUNTER
There are two types of counter/timer in 8051.These counter/timers are name as Timer/Counter
0 and Timer/Counter 1. Each one can be used as either Timer or Counter. 16 bit timer register
are used for counting in timer operation or counter operation. Clock pulses are counted in Timer
operation and external events are counted in counter operation.

Q2 (e) What do you mean by assembly language programming? What is the function of JUMP
and CALL instruction?

ANS. In computer programming, assembly language (alternatively assembler

language or symbolic machine code), often referred to simply as Assembly and commonly
abbreviated as ASM or asm, is any low-level programming language with a very strong
correspondence between the instructions in the language and the architecture's machine
code instructions. Assembly language usually has one statement per machine instruction but
constants, comments, assembler directives, symbolic labels of, e.g., memory
locations, registers, and macros are generally also supported.
JUMP or GOTO is a transfer of the control to another location and the control does not
automatically return to the point from where it is called.

JMP Instruction:

Unconditional JMP Instructions:

• This instruction enables the programmer to set up a continuous loop.

• When this instruction is executed then PC content will become a specified
address and the next instruction execution will start from the given address
memory location.
• 3-byte instruction
• Immediate addressing mode
• 3 MC
• 10 T-states
Conditional JMP Instructions:

• This instruction allows the microprocessor to make decisions based on certain

conditions indicated by the flags.
• The conditional jump instruction checks the flag conditions and makes
decisions to change or not to change the sequence of a program.
• Out of five flags, 4 (CY, Z, S, and P) flags are used by conditional JMP, but the
AC flag is not used.
On the other hand, a CALL or procedure/function call returns to the point from where it is
called. Due to this difference in their nature, languages typically make use of a stack and a
stack frame is pushed to "remember" the location to come back for each procedure called. This
behaviour applies to recursive procedures too. In case of tail recursion, there is however no
need to "push" a stack frame for each call.
⇒CALL Instruction:

• It is used in the main program to call a subroutine.

• When a subroutine is called, the contents of PC, which is the address of the
instruction following the CALL instruction, is stored on the stack and the
program execution is transferred to the subroutine address.
Unconditional CALL Instructions:

• When it is executed, the microprocessor will store the address of the next
instruction in STACK and the PC is located with a subroutine address.
• 3-byte instruction
• Immediate/Register indirect mode
• 5 MC
• 18 T-States
• No flags are affected
Conditional CALL Instructions:

• In this case, the program is transferred to the subroutine if the condition is met
and this time it requires 5 MC and 18 T-States.
• If the condition is not met then the main program is continued and it requires 2
MC and 9 T-states.
• In this instruction, all flags are used except the AC flag.

Q3(a) Discuss the various addressing modes of 8085 in detail.

ANS. Addressing Modes of 8085 Microprocessor:

The different ways that a microprocessor can access data are referred to as addressing modes.
Addressing Modes of 8085 Microprocessor are :

1. Immediate Addressing Mode in 8085

2. Register Addressing Mode in 8085
3. Direct Addressing Mode in 8085
4. Indirect Addressing Mode in 8085
5. Implied Addressing Mode in 8085
1. Immediate Addressing Mode in 8085:

In an Immediate Addressing Modes of 8085 Microprocessor, 8 or 16 bit data can be specified

as a part of instruction. In 8085, the instructions having ‘I’ letter fall under this category. ‘I’
indicates immediate addressing mode.
2. Register Addressing Mode in 8085:

Another Types of Addressing Modes in 8085 is Register Addressing Mode in 8085 which
specifies the source operand, destination operand, or both to be contained in an 8085 registers.
This results in faster execution, since it is not necessary to access memory locations for
operands.

3. Direct Addressing Mode in 8085:

The Direct Addressing Mode in 8085 specifies the 16 bit address of the operand within the
instruction itself. The second and third bytes of instruction contain this 16 bit address.

4. Indirect Addressing Mode in 8085:

In Indirect Addressing Mode in 8085, the memory address where the operand located is
specified by the contents of a register pair.

Example: LDAX B

5. Implied Addressing Mode in 8085:

In Implied Addressing Mode in 8085, opcode specifies the address of the operands.

Example: CMA

Q3(b) Explain the classification of the instruction set of 8085 microprocessor with suitable
examples.
ANS.Introduction of Instruction An instruction is a binary pattern designed inside a
microprocessor to perform a specified function. In another word, we can say An
instruction is a command given task on specified data.

Each instruction has two parts:

1. One is the task to be performed, called the “operation code” (OPCODE).

2. Second is the data to be operated on called the “OPERAND”.
The operand ( or data) may include 8-bit or 16-bit data, on the internal register, a memory
location, or an 8-bit or 16-bit address.

Introduction of Instruction Sets

The instruction set is a collection of Instructions of Microprocessor, that determines what

functions that microprocessor can perform.

In data transfer, the contents of the source are not destroyed; only the contents of the destination
are changed.

An I/O device can transfer or receive data from the accumulator but not from other registers
(except for the memory-mapped I/O device).

Arithmetic and logical operations are performed with the contents of the accumulator, and the
results are stored in the accumulator.

Any register including memory can be used for increment and decrement.

A program sequence can be changed either conditionally or by testing for given data conditions.

In some instructions, data is implied. Most instructions of this type operate on the content of
the accumulator.

Classification of Instruction Set of 8085

Types of Instruction set of 8085 based on Length of Word size

1-byte or One-word Instruction set of 8085

• A one-byte instruction includes the opcode and the operand in the same byte.
• Examples of this type are:
• MOV A, B
• ADD B
• RAL
• CMA, etc.
For 1-byte Instruction:

Task Opcode Operand

Copy the contents of the

MOV C, A
accumulator in Register C

Add the contents of the register B to

ADD B
the contents of the accumulator

Invert (Complement) each bit in the

CMA
accumulator

• The above instructions are 1-byte instructions performing three different tasks.
• In the first instruction, both operand registers are specified.
• In the second instruction, operand B is specified and the accumulator is
assumed.
• Similarly, in the third instruction, the accumulator is assumed to be the implicit
operand.
 • These instructions are stored in an 8-bit binary format in memory; each requires
one memory location.
2-byte or 2-word Instruction set of 8085

• In a 2-byte instruction, the 1st-byte specifies the opcode and the 2nd-byte
specifies the operand.
• MVI B, 05
• IN 01 etc.
For 2-byte Instruction:

Task Opcode Operand Hex Code

Load an 8-bit data byte in

MVI A, Data 1st byte, data 2nd by
the accumulator

• Assume the data byte is 32H. The assembly language instruction is written as:
• Mnemonics: MVI A, 32H
• This instruction would require two memory locations to store n memory.
3-byte or 3-word Instruction set of 8085

• In a 3-byte instruction, the 1st byte specifies the opcode, and the following two
bytes specify the 16-bit address such that the 2nd byte is a low order address
and the 3rd-byte is high order address.
• LXI H, 2400H
• LDA 2500H
• JMP 2085H etc.
For 3-byte Instruction:

Task Opcode Operand Hex Code

Transfer the program

C3 is 1st byte, 85
sequence to the memory JMP 2085 H
byte, and 20 3rd byte
location 2085H

• This instruction would require three memory locations to store in the memory.
Types of Instruction set of 8085 based on Addressing Modes:

1.Direct Addressing Mode Instruction set of 8085

• In this instruction set, the direct address contains the address of operand within
the instruction itself.
• LDA 2600 H
• IN 05
• OUT 07
• STA 2700 H
2.Register Addressing Mode Instruction set of 8085

• In this type of instruction set, operands will be present in the micro -process
registers.
• MOV A, B
• ADD B
• SUB C
3.Register Indirect Addressing Mode Instruction set of 8085

•In this type of instruction, the operands will present in memory (M) and the
address of memory is present register pair.
• It is also called “indirect addressing mode type instruction set”.
• MOV A, M
• ADD M
• LDAX B
4.Immediate Addressing Mode Instruction set of 8085

• In this type, the operand and data are specified within the instruction itself.
• In other words, we can say, this type of instruction has an operand field rather
than an address field.
• MVI A, 25
• ADI 36
5.Implicit Addressing Mode Instruction set of 8085

• If operations of the microprocessor are performed by accumulator alone or

machine control instructions, then it contains an implied addressing type.
• e.g. CMA, RAL, DAA
1.Data Transfer Instruction set of 8085

In this group, the data in transfer,

• From register to register

• Between memory and register
• Between I/O and accumulator
• Load an 8-bit number in a register
• Load 16-bit number in a register pair.
Instruction Addressing T- Machine Affected Bytes
Meaning Example
Set Mode States Cycle Flags Instruc

MOV r1, r2 Register

Move content of
one register to MOV A, B addressing 4T 1 MC None 1-byte
[r1] ← [r2] another register mode

MOV r, M Register
Move content of
indirect
memory to MOV B, M 7T 2 MC None 1-byte
addressing
[r] ← [M] or register
mode
[r] ←
[[H,L]]

MOV M, r
Register
Move content of
[M] ← [r] or indirect
register to MOV M, C 7T 2 MC None 1-byte
addressing
memory
[[H,L]] ← mode
[r]

MOV r, data Move Immediate

immediate data MOV A, 05H addressing 7T 2 MC None 2-byte
[r] ← data to register mode

LXI rp, 16-

bit data

[rp] ← 16- LXI H,

Load register Immediate
bit data; 2800H, i.e. [L]
pair addressing 10T 3 MC None 3-byte
immediately ← [00],[H] ← mode
[rh] ← 8 [28]
MSBs of
data,[rl] ← 8
LSBs of data

LDA
address Load direct
accumulator LDA 2400H addressing 13T 4 MC None 3-byte
[A] ← direct mode
[[address]]

STA address
store direct
accumulator STA 2000H addressing 13T 4 MC None 3-byte
[[address]] direct mode
← [A]

LHLD
address direct
Load H-L pair
direct LHLD 2500H addressing 16T 5 MC None 3-byte
[L] ← mode
[[address]],
 [H] ←
[[address +
1]]

SHLD
address
direct
store H-L pair
[[address]] direct SHLD 2500H addressing 16T 5 MC None 3-byte
← mode
[L],[[address
+ 1]] ← [H]

LDAX rp Register
Load
indirect
accumulator LDAX B 7T 2 MC None 1-byte
addressing
[A] ← [[rp]] indirect
mode

STAX rp Register
store
indirect
accumulator STAX D 7T 2 MC None 1-byte
addressing
[[rp]] ← [A] indirect
mode

XCHG Exchange the

Register
content of H-L
addressing
[H-L] ↔ [D- pair with D-E XCHG 4T 1 MC None 1-byte
mode
E] pair

LXI H ,
2400H
MVI M, data
MVI M, Register
Move
08 indirect
[[H-L]] ← immediate data
addressing 10T 3 MC None 2-byte
[data] or [M] to memory
mode
← [data] HLT

2.Arithmetic Group Instruction set of 8085

In this group, the data is performed as addition, subtraction, increment (add 1), decrement
(subtract 1), etc.
The arithmetic operations implicitly assume that the content of the accumulator is one of the
operands.

The results of the arithmetic operations are stored in the accumulator, thus the previous content
of the accumulator is altered.

The flags are modified to reflect the data conditions of an operation.

The content of a register is not changed as a result of an arithmetic operation.

In the add operation, if the sum is larger than 8-bit, CY is set.

The subtraction operation is performed by using 2’s complement method and CY is

complemented after subtraction.

If a subtraction results in a negative number, the answer is in 2’s complement and CY is set.

In unsigned arithmetic operations, the sign flag(S) should be ignored.

The instructions INR (Increment) and DCR (Decrement) are special cases of arithmetic
operations.

Instruction Addressing T- Machine Affected

Meaning Example
Set Mode States Cycle Flags

ADD r
Add register to Register
the ADD B addressing 4T 1 MC All
[A]← [A] + [r] accumulator mode

ADC r
Add register
Register
with carry to
[A]← [A] + [r] ADC D addressing 4T 1 MC All
the
+ [C] mode
accumulator
ADD M

[A]← [A] + Register

[M] or Add memory indirect
ADD M 7T 2 MC All
to accumulator addressing
mode
[A]← [A] +
[[H-L]]

ADC M

[A]← [A] + Add memory Register

[M] + [C] or indirect
with carry to ADC M 7T 2 MC All
addressing
accumulator
mode
[A]← [A] +
[[H-L]] + [C]

ADI data
Add
Immediate
immediate
[A]← [A] + data to the ADI 08H addressing 7T 2 MC All
data mode
accumulator

ADI data Add

immediate Immediate
[A]← [A] + data with carry ACI 08H addressing 7T 2 MC All
data + [C] to the mode
accumulator

SUB r Subtract
Register
register from
SUB B addressing 4T 1 MC All
[A]← [A] – [r] the
mode
accumulator
SBB r Subtract
register from Register
[A]← [A] – [r] the SBB B addressing 4T 1 MC All
– [C] accumulator mode
with borrow

SUB M

[A]← [A] – Subtract Register

[M] or memory from indirect
SUB M 7T 2 MC All
the addressing
[A]← [A] – accumulator mode
[[H-L]]

SBB M
Subtract
[A]← [A] – memory from
Register
[M] – [C] or the SBB M
indirect
7T 2 MC All
addressing
accumulator
[A]← [A] – mode
with borrow
[[H-L]] – [C]

SUI data
Subtract
Immediate
immediate
[A]← [A] – SUI 01H addressing 7T 2 MC All
data from the
data mode
accumulator

SBI data Subtract

immediate Immediate
[A]← [A] – data from the SBI 01H addressing 7T 2 MC All
data – [C] accumulator mode
with borrow
INR r
Increment Register
All except
register INR D addressing 4T 1 MC
[r]← [r] + [01] CY
content by 1 mode

INR M

[M]← [M] + Increment the Indirect

[01] or Register All except
memory INR M 10T 3 MC
addressing CY
content by 1
[[H-L]]← [[H- mode
L]] + [01]

INX rp
Increment the
Register
content of
[rp]← [rp] + register pair by INX D addressing 6T 1 MC None
[0001] mode
1

DCR r
Decrement Register
All except
register DCR D addressing 4T 1 MC
[r]← [r] – [01] CY
content by 1 mode

DCR M

[M]← [M] – Decrement the

Indirect
[01] or Register All except
memory DCR M 10T 3 MC
addressing CY
content by 1
mode
[[H-L]]← [[H-
L]] – [01]
 DCX rp
Decrement the
Register
content of
[rp]← [rp] – DCX D addressing 6T 1 MC None
register pair by
[0001] mode
1

Decimal
Implicit
DAA adjust
DAA addressing 4T 1 MC All
accumulator
mode
after addition

DAD rp
Double Register
[[H-L]]← [[H- addition DAD H addressing 10T 3 MC only CY
L]] + [rp] register pair mode

3.Logical Group Instruction set of 8085

The instruction set of this group performs AND, OR, EXOR operations, compare, rotate or
take the complement of data in register or memory.

The process of performing logic operations through the software instructions is slightly
different from the hardwired logic.

Logic operations are performed n relation to the content of the accumulator.

Logic operations simulate eight 2-input gates ( or inverters).

The sign, zero (and parity) flags are modified to reflect the status of operations. The carry
flag is reset. However, the NOT operation does not affect any flags.

After a logic operation has been performed, the answers are placed in the accumulator replacing
the original content of the accumulator.

The logic operations cannot be performed directly with the content of two registers.

The individual bits in the accumulator can be set or reset using logic instructions.

Instruction Addressing T- Machine Affected

Meaning Example
Set Mode States Cycle Flags
ANA r
AND register Register All and
with the ANA B addressing 4T 1 MC AC=1,
[A] ← [A] ∧ [r] accumulator mode CY=0

ANA M

[A] ← [A] ∧ AND memory

Register
All and
[M] or indirect
with the ANA M 7T 2 MC AC=1,
addressing
accumulator CY=0
mode
[A] ← [A] ∧
[[H-L]]

ANI data
AND
Immediate All and
immediate data
[A] ← [A] ∧ ANI 01H addressing 7T 2 MC AC=1,
with the
data mode CY=0
accumulator

ORA r
OR register Register All and
with the ORA B addressing 4T 1 MC AC=0,
[A] ← [A] ∨ [r] accumulator mode CY=0

ORA M

[A] ← [A] ∨ OR memory

Register
All and
[M] or indirect
with the ORA M 7T 2 MC AC=0,
addressing
accumulator CY=0
mode
[A] ← [A] ∨
[[H-L]]

ORI data
OR immediate Immediate All and
[A] ← [A] ∨ data with the ORI 01H addressing 7T 2 MC AC=0,
data accumulator mode CY=0

XRA r
EXOR register Register All and
[A] ← [A] with the XRA B addressing 4T 1 MC AC=0,
” data accumulator mode CY=0
XRA M

[A] ← [A] ” EXOR Register

All and
[M] or memory with indirect
XRA M 7T 2 MC AC=0,
the addressing
CY=0
accumulator mode
[A] ← [A] ”
[[H-L]]

XRI data
EXOR
Immediate All and
immediate data
[A] ← [A] ∨ XRI 01H addressing 7T 2 MC AC=0,
with the
data mode CY=0
accumulator

CMA
Complement Implicit
the CMA addressing 4T 1 MC None
[A] → [Ā] accumulator mode

Compare Register
CMP r register with CMP B addressing 4T 1 MC All
accumulator moder

CMP M
Register
Compare
indirect
[A] ← [A] – memory with CMP M 7T 2 MC All
addressing
[M] accumulator
mode

CPI data
Compare
Immediate
immediate data
[A] ← [A] – CMP 01H addressing 7T 2 MC All
with
[data] mode
accumulator

CMC
No flag
Complement
CMC 4T 1 MC except CY
[CS] ← [CS’] the carry status
flag

STC
No flag
Set carry status STC 4T 1 MC
[CS] ← 1 except CY
 RLC
Rotate
accumulator
[An+1] ← [An]
left. The Implicit
content of the addressing 4T 1 MC only CY
[Ao] ← [A7] accumulator is mode
rotated left by
[CY] ← [A7] one bit.

RRC
Rotate
accumulator
[An] ← [An+1]
right. The Implicit
content of the RRC addressing 4T 1 MC only CY
[A7] ← [A0] accumulator is mode
rotated right by
[CY] ← [A0] one bit.

Rotate
RAL
accumulator
left through
[An+1] ← [An] carry. The Implicit
content of the RAL addressing 4T 1 MC only CY
[CS] ← [A7] accumulator is mode
rotated left one
bit through
[A0] ← [CS]
carry.

Rotate
RAR
accumulator
right through
[An] ← [An+1] carry. The Implicit
content of the RAR addressing 4T 1 MC only CY
[CS] ← [A0] accumulator is mode
rotated right
one bit through
[A7] ← [CS]
carry.

4.Branch Group Instruction set of 8085

The Branch Instructions are the most powerful instructions because they allow the
microprocessor to change the sequence of a program, either unconditionally or under certain
test conditions.

These instructions are the key to the flexibility and versatility of a computer.

These are classified into 3 categories:

 1. JUMP instructions
2. CALL and RETURN instructions
3. RESTART instructions.
⇒JMP Instruction:

Unconditional JMP Instructions:

• This instruction enables the programmer to set up a continuous loop.

• When this instruction is executed then PC content will become a specified
address and the next instruction execution will start from the given address
memory location.
• 3-byte instruction
• Immediate addressing mode
• 3 MC
• 10 T-states
Conditional JMP Instructions:

• This instruction allows the microprocessor to make decisions based on certain

conditions indicated by the flags.
• The conditional jump instruction checks the flag conditions and makes
decisions to change or not to change the sequence of a program.
• Out of five flags, 4 (CY, Z, S, and P) flags are used by conditional JMP, but the
AC flag is not used.
Opcode Operand Description

JC 16-bit Jump on carry ( if result generates carry and CY=1 )

JNC 16-bit Jump on no carry ( CY=0 )

JZ 16-bit Jump on zero ( if result is zero and Z=1 )

JNZ 16-bit Jump on no zero ( Z=0 )

JP 16-bit Jump on plus ( if D 7=0 and S=0 )

JM 16-bit Jump on minus ( if D 7=1 and S=1 )

JPE 16-bit Jump on even parity ( P=1 )

JPO 16-bit Jump on add parity ( P=0 )

⇒CALL Instruction:
 • It is used in the main program to call a subroutine.
• When a subroutine is called, the contents of PC, which is the address of the
instruction following the CALL instruction, is stored on the stack and the
program execution is transferred to the subroutine address.
Unconditional CALL Instructions:

• When it is executed, the microprocessor will store the address of the next
instruction in STACK and the PC is located with a subroutine address.
• 3-byte instruction
• Immediate/Register indirect mode
• 5 MC
• 18 T-States
• No flags are affected
Conditional CALL Instructions:

• In this case, the program is transferred to the subroutine if the condition is met
and this time it requires 5 MC and 18 T-States.
• If the condition is not met then the main program is continued and it requires 2
MC and 9 T-states.
• In this instruction, all flags are used except the AC flag.
Opcode Operand Description

CC 16-bit Call subroutine if carry flag is set ( CY = 1)

CNC 16-bit Call subroutine if carry flag is reset (CY = 0)

CZ 16-bit Call subroutine if zero flag is set ( Z=1 )

CNZ 16-bit Call subroutine if zero flag is reset ( Z=0 )

CM 16-bit Call subroutine if sign flag is set ( S=1, negative number)

CP 16-bit Call subroutine if sign flag is reset ( S=0, positive number)

CPE 16-bit Call subroutine if parity flag is set ( P=1, even parity)

CPO 16-bit Call subroutine if parity flag is reset ( P=0, odd parity)

⇒RETURN Instruction:

• It is used at the end of the subroutine to return to the main program.

 • When RET instruction is executed as the end of the subroutine, the memory
address stored on the stack is retrieved, and the sequence of execution is
resumed in the main program.
Unconditional RET Instructions:

• It will change the program sequence from subroutine to the main program.
• 1-byte instruction
• Implicit addressing mode
• 3 MC
• 10 T-states
• No flags are affected.
Conditional RET Instructions:

• In this case, the sequence of the program returns to the main program if the
condition is met and at this time it requires 3 MC and 12 T-States.
• If the condition is not met then the sequence of the program is continued in the
subroutine and it requires 1-MC and 6 T-states.
• In this instruction, all flags are used except the AC flag.
Opcode Operand Description

RC 16-bit Return if carry flag is set (CY=1)

RNC 16-bit Return if carry flag is reset (CY=0)

RZ 16-bit Return if zero flag is set (Z=1)

RNZ 16-bit Return if zero flag is reset (Z=0)

RM 16-bit Return if sign flag is set (S=1, negative number)

RP 16-bit Return if sign flag is reset (S=0, positive number)

RPE 16-bit Return if parity flag is set (P=1, even parity)

RPO 16-bit Return if parity flag is reset (P=0, odd parity)

5.Stack, I/O and Machine Control Group Instruction set of 8085

The stack in an 8085 microprocessor is a group of memory locations in the R/W memory that
is used for the temporary storage of binary information during the execution of the program.

PUSH, POP, SPHL, XHTL are the example of instruction of stack group.
IN, OUT are the example of I/O group.

NOP, EI, D, SIM, RIM, HLT are examples of the machine control groups.

Addressing T- Machine Affected

Instruction Set Meaning Example
Mode States Cycle Flags

PUSH rp

[[SP-1]] ← [rh] Push the Register

content of indirect
PUSH H 12T 3 MC None
[[SP-2]] ← [rl] register pair to addressing
stack mode
[SP] ← [SP] – 2

POP rp

[rl] ← [[SP]] Pop the

content of Register
[rh] ← [[SP] + register pair to indirect
POP H 10T 3 MC None
1] stack which addressing
was saved mode
from the stack
[SP] ← [SP] +
2

SPHL
Move the Register
content of H-L SPHL addressing 6T 1 MC None
[H-L] → [SP] pair to SP mode

XTHL
Register
[L] → [[SP]] Exchange
indirect
stack top with XTHL 16T 5 MC None
addressing
H-L pair
[H] → [[SP] + 1 mode
]

IN 05
IN Port address
Input to Direct
accumulator addressing 10T 3 MC None
[Accumulator]
[A] ← [Port] from I/O Port mode
← [[05]]
 OUT Port OUT 05
Output from
address Direct
the None
accumulator to [[05]] ← addressing 10T 3 MC
[Port] ← [A] [Accumulator] mode
I/O Port

Implicit
HLT Halt HLT addressing 5T 1 MC None
mode

No operation

NOP Read interrupt

mask
RIM
Set interrupt All implicit
SIM mask addressing all 4T all 1 MC None
mode
DI DIsable
interrupt
EI
Enable
Interrupt

4(a) Explain minimum and maximum operating modes of 8086 with timing diagram.

ANS. Timing diagram :

The working of min mode can be easily understood by timing diagrams.
• All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is
given by processor in the T1 state. It is available on the bus for one T-state.
• In T2, the bus is tristated for changing the direction of the bus( in the case of a
data read cycle.)
• The data transfer takes place between T 3 and T4.
• If the addressed device is slower, then the wait state is inserted between T 3 and
T4.
 Opcode fetch or read timing diagram
• At T1 state ALE =1 ,this indicates that a valid address is latched on the address
bus and also M / IO’= 1, which indicates the memory operation is in progress.
• In T2, the address is removed from the local bus and is sent to the addressed
device. Then the bus is tristated.
• When RD’ = 0 , the valid data is present on the data bus.
• During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates
that the data is received.
• During T3, data is put on the data bus and the processor reads it.
• The output device makes the READY line high. This means the output device
has performed the data transfer process. When the processor makes the read
signal to 1, then the output device will again tristate its bus drivers.
 Write memory cycle
• At T1 state ALE =1 ,this indicates that a valid address is latched on the address
bus and also M / IO’= 1, which indicates the memory operation is in progress.
• In T2, the processor sends the data to be written to the addressed location.
• The data is buffered on the bus until the middle of T4 state.
• The WR’=0 becomes at the beginning of T2.
• The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O
word.
• During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which indicates
that the data is transferred by the processor to the addressed device.
Timing diagram :
The working of min mode can be easily understood by timing diagrams.
• All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is
given by processor in the T1 state. It is available on the bus for one T-state.
• In T2, the bus is tristated for changing the direction of the bus( in the case of a
data read cycle.)
• The data transfer takes place between T 3 and T4.
• If the addressed device is slower, then the wait state is inserted between T 3 and
T4.
 Opcode fetch or read timing diagram
• At T1 state ALE =1 ,this indicates that a valid address is latched on the address
bus and also M / IO’= 1, which indicates the memory operation is in progress.
• In T2, the address is removed from the local bus and is sent to the addressed
device. Then the bus is tristated.
• When RD’ = 0 , the valid data is present on the data bus.
• During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates
that the data is received.
• During T3, data is put on the data bus and the processor reads it.
• The output device makes the READY line high. This means the output device
has performed the data transfer process. When the processor makes the read
signal to 1, then the output device will again tristate its bus drivers.
 Write memory cycle
• At T1 state ALE =1 ,this indicates that a valid address is latched on the address
bus and also M / IO’= 1, which indicates the memory operation is in progress.
• In T2, the processor sends the data to be written to the addressed location.
• The data is buffered on the bus until the middle of T4 state.
• The WR’=0 becomes at the beginning of T2.
• The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O
word.
• During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which indicates
that the data is transferred by the processor to the addressed device.

(b) Draw and explain the internal block diagram of 8086.

The Internal Block Diagram of 8086 Microprocessor is shown below.

The functional block diagram of 8086 is divided into two functional units.

(1) Bus Interface Unit and (2) Execution Unit

They are explained below.

(1) Bus Interface Unit:

Bus Interface Unit is a gate (enhance) interface between peripheral devices and Processor.
Through the bus interface only, processor can send and receive data. The bus interface unit
contains

(a) Instruction Queue

(b) Segment Registers
(c) Instruction Pointers

(a) Instruction Queue

In 8086 Processor, instruction queue is a 6 byte register used to store permanent data from the
Input/Output (I/O) devices or processor. The queue operates in the principle of First In First
Out (FIFO) principle. i.e., the first data is fetched and that data will be taken out firstly.

(b) Segment Register:

In 8086 Processor, there are four segment registers. They are

ES – Extra Segment
CS – Code Segment
DS – Data Segment
SS – Stack Segment

The maximum memory access of 8086 processor is 1 MB. Each segment has some
predefined functions.

In 8086 processor, each segment has a capacity of 64 KB. So the four segments will store 256
KB of memory locations. The remaining memory locations are free and in these locations,
user can perform any other processes. These four segment registers will keep the base address
of the corresponding segment.

(c) Instruction Pointer (IP):

Instruction pointer will give the next address of the instruction to be executed. Instruction
Point cannot be used for other purposes.

(2) Execution Unit:

The execution unit contains

(a) Control Unit

(b) Instruction Decoders
(c) ALU
(d) General Purpose Registers
(e) Flag Registers

Address Generation:

The I/O processor can receive data from the memory only, if that data should goes out
through the address generation.

General Purpose Registers:

AX, BX, CX, DX, SP, BP, SI, DI are General Purpose Registers.
1. AX register (Accumulator):

AX register can save 16 bit data only.

2. BX register:

BX register is the base register. It is used to save the base data (value).

3. CX register:

CX register is code register (Count Register)

4. DX Register:

DX register is data register. DX register is used to store datas.

5. SP (Stack Pointer):

Stack Pointer keeps the top of the stack. The stack pointer operates in the principle of Last In
First Out (LIFO). Since one location can store only 8 bit data, in order to store a 16 bit data,
two memory locations are needed. So the stack pointer will decreased by two memory
locations, if a data is taken.

6. BP (Base Pointer):

Base pointer is used to store the base address of the memory or stack.

7. SI (Source Index):

Source Index is used to hold the index value of source operand for string instructions.

8. DI (Destination Index):

DI is used to hold the index value of destination operand for string instructions.
General purpose registers are used for holding data, intermediate results, counters, mode of
addressing and also for storing effective address.
Flag Registers:

The three control flags are,

1. Trap Flag (TF)
2. Interrupt flag (IF)
3. Direction Flag (DF)

Instruction Format,

15 14 13 12 11 10 9 8 7 6 5 4 3
2 1 0
U U U U CF DF IF TF SF ZF U AF U PF V CF

Symbolic Representation,

Q5 (a) Draw and explain block diagram of IC-8253/54.

ANS. The Intel 8253 and 8254 are Programmable Interval Timers designed for
microprocessors to perform timing and counting functions using three 16 -bit registers. Each
counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a c ounter,
a 16-bit count is loaded in its register. On command, it begins to decrement the count until it
reaches 0, then it generates a pulse that can be used to interrupt the CPU.
Features of 8253 / 54
The most prominent features of 8253/54 are as follows −
• It has three independent 16-bit down counters.
• It can handle inputs from DC to 10 MHz.
• These three counters can be programmed for either binary or BCD count.
 • It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which allows
the user to check the count value, the programmed mode, the current mode, and
the current status of the counter.
8254 Architecture
The architecture of 8254 looks as follows −

8254 Pin Description

Here is the pin diagram of 8254 −
In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal
- OUT.
Data Bus Buffer
It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system
data bus. It has three basic functions −
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.
Read/Write Logic
It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 & A1. In the peripheral I/O
mode, the RD and WR signals are connected to IOR and IOW, respectively. In the
memorymapped I/O mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A 0 and A1 of the 8253/54, and CS is
tied to a decoded address. The control word register and counters are selected according to the
signals on lines A0 & A1.

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection
Control Word Register
This register is accessed when lines A 0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation. Following
table shows the result for various control inputs.
 A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation
Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either binary
or BCD. Its input and output is configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters without disturbing
the actual count in process.

Q5 (b) Explain 8255 PPI in detail. And discuss its mode 1 and mode 2 operation.
ANS. The 8255 PPI is a programmable peripheral interface device.
• It is a general-purpose programmable parallel I/O device.
• It contains 3 I/O ports which can be programmed in different modes.
• To program the function to all three i/O ports t contains a register called
control registers. The control register defines the function of each I/O port and
in which mode they should operate.
• 8055 PPI is general purpose in nature and provides many facilities for
connecting different devices. So it is used frequently in different
applications.of 8255 PPI
• It is a programmable parallel I/O device.
• It contains 24 programmable I/O pins arranged as 2-8 bit ports and 2-4 bit
ports.
• It has 3, 8-bit ports: Port A, Port B, and Port C, which are arranged in two
groupss of 12 pins.
• Fully compatible with Intel microprocessor families.
• TTL is compatible.
• Direct bit set/reset capability is available for port C.
• Improved DC driving capability.
• It can operate in 3 Modes:
1. Mode 0: Simple I/O
2. Mode 1: Strobed I/O
3. Mode 2: Strobed bi-directional I/O
Pin Configuration of 8255 PPI
The pin configuration of 8255 PPI (Programmable Peripheral Interface) is as shown in the
figure below:

PA0-
I/O Port A pins
PA7

PB0-PB7 I/O Port B pins

PC0-PC7 I/O Post C pins

D0-D7 I/O Data pins

RESET I Reset input

RD I Read input

WR I Write input
A0-A1 I Address pins

CS I Chip select

VCC-
I +5 V supply ground
GND

Symbol Name Function

These are 8-bit bi-directional data bus lines,

D0-D7 Data Bus connected to the system data bus for data
transfer between CPU and 8255.

These are input, active HIGH address lines

Chip
CS used to distinguish different ports of 8255 such
select
as Port A, Port B, Port C, and Control register.

This is an active low input signal used in

RD Read coordination with another signal to send data to
the CPU through data lines.

This is an active low input signal used in

WR Wite coordination with another signal to send data to
8255.

These are input, active HIGH address lines

Address
A0-A1 used to distinguish different ports of 8255 such
lines
as Port A, Port B, Port C, Control register.

This is an active HIGH input signal used to

reset 8255. When 8255 is reset, it clears the
RESET Reset
control word register and all ports are set to
input mode.

These are 8-bit bidirectional I/O pins used to

Port A
PA0- send data to the peripheral or to read data from
pins 0 to
PA7 the peripheral. The contents are transferred
7
to/from Port A.
 Port B
These are 8-bit bidirectional I/O pins used the
PB0-PB7 pins 0 to
same as PA0-PA7
7

These are 8-bit bidirectional I/O pins. These

Port C lines are divided into 2 sections i.e. PC0-
PC0-PC7 pins 0 to PC3 and PC4-PC7. These two sections can be
7 individually used to transfer 4 bits of data from
two separate port C sections.

iagram

The block diagram of 8255 PPI is shown in the figure below:

It contains the following blocks

1. Data bus buffer

2. Read/Write control logic
3. Group A and Group B control
4. Port A and Port B
5. Port C

1. BSR Mode

• The BSR mode is a port C bit set/reset mode.

• The individual bit of port C can be set or reset by writing the control word in
the control register.
• The control word format of BSR mode is as shown in the figure below:
 • The pin of port C is selected using bit select bits [b b b] and set or reset is
decided by bit S/R.
• The BSR mode affects only one bit of port C at a time.
• The bit set using BSR mode remains set unless and until you change the bit.
So to set any bit of port C, the bit pattern is loaded in the control register.
• If a BSR mode is selected, it will not affect the I/O mode.
2. I/O Modes

There are three I/O modes of operation:

1. Mode 0: Basic I/O

2. Mode 1: Strobed I/O
3. Mode 2: Bidirectional I/O
I/O modes are programmed using a control register.

The function of each bit is as follows:

1. D7: When the bit D7=1 then I/O mode is selected, if D7=0 then BSR mode is
selected. The function of bits D0 to D6 is dependent on mode.
 2. D6 and D5: In I/O mode the bit D6 and D5 specify the different I/O modes for
group A.
3. D4 and D3: In I/O mode the bits D4 and D3 select the port function for groups
A. If these bits =1 the respective port specified is used as the input port. But if
bit=0, the port is used as the output port.
4. D2: In I/O mode the bit D2 specifies the different I/O modes for group B.
5. D1 and D0: In I/O mode the bits D1 and D0 select the port function for group
B. If these bits =1 the respective port specified is used as the input port. But if
bit=0, the port is used as the output port.
8255 PPI Applications

8255 PPI is the most widely used chip for many applications:

• LED / Relay Interface

• Display Interface
• Stepper Motor Interface
• Lift Controller etc.
• Keyboard Interface
• ADC / DAC Interface
• Traffic Signal Controller
Mode 1 is the strobed input/output mode. This mode is similar to mode 0, but includes
additional control signals to enable latching of input data and/or output data.
Mode 2 is the bidirectional mode. In this mode, Port A and Port B are configured as
bidirectional I/O ports, while Port C is configured as a control p ort for setting various
operational modes.
Each of these operating modes can be further customized through programming of various
control registers, allowing for flexible and efficient interfacing with a wide range of
peripheral devices.
There are 2 modes in 8255 microprocessor: 1. Bit set reset (BSR) mode – This mode is
used to set or reset the bits of port C only, and selected when the most significant bit (D7)
in the control register is 0. Control Register is as
follows:
 This mode affects only one bit
of port C at a time because, as user set the bit, it remains set until and unless user changes
it. User needs to load the bit pattern in control register to change the bit. 2. Input/output
mode (I/O) – This mode is selected when the most significant bit (D7) in the control
register is 1.
• Mode 0 – Simple or basic I/O mode: Port A, B and C can work either as input
function or as output function. The outputs are latched but the inputs are not
latched. It has interrupt handling capability.
• Mode 1 – Handshake or strobed I/O: In this either port A or B can work and
port C bits are used to provide handshaking. The outputs as well as inputs are
latched. It has interrupt handling capability. Before actual data transfer there is
transmission of signal to match speed of CPU and printer. Example: When CPU
wants to send data to slow peripheral device like printer, it will send
handshaking signal to printer to tell whether it is ready or not to transfer the
data. When printer will be ready it will send one acknowledgement to CPU then
there will be transfer of data through data
 bus.

• Mode 2 – Bidirectional I/O: In this mode only port A will work, port B can
either is in mode 0 or 1 and port C bits are used as handshake signal. The
outputs as well as inputs are latched. It has interrupt handling capab ility. Control
Register is as
follows:

The most significant bit (D7) is 1 for the I/O mode and 0 for the BSR mode. D6
& D5It is used to set the port A

mode. D4 is
used to tell whether port A is taking input or displaying the result. If it is 1 then
it is taking input otherwise displaying output. D3 is used to tell whether port C
higher bits is taking input or displaying the result. If it is 1 then it is taking input
otherwise displaying output. D2 tells the mode of port B. If it is 0 then port B is
in m0 mode otherwise in m1 mode. D1 is used to tell whether port B is taking
 input or displaying the result. If it is 1 then it is taking input otherwise
displaying output. D0 is used to tell whether port C lower bits is taking input or
displaying the result. If it is 1 then it is taking input otherwise displaying output.
When 8255 microprocessor is reset, it will clear the control word register contents, setting
all the ports to input mode.

Q6 (a) Draw and explain the pin configuration of 8051

ANS. The 8051 microcontroller is a popular 8-bit microcontroller widely used in embedded
systems. It is a single-chip microcontroller with a Harvard architecture that includes a CPU,
RAM, ROM, and several peripherals. The 8051 microcontroller has a 40-pin dual in-line
package (DIP) that provides various inputs and outputs for communication with external
devices.
8051 microcontroller is a 40 pin Dual Inline Package (DIP). These 40 pins serve different
functions like read, write, I/O operations, interrupts etc. 8051 has four I/O ports wherein
each port has 8 pins which can be configured as input or output depending upon the logic
state of the pins. Therefore, 32 out of these 40 pins are dedicated to I/O ports. The rest of
the pins are dedicated to VCC, GND, XTAL1, XTAL2, RST, ALE, EA’ and PSEN’. Pin
diagram of 8051 microprocessor is as given below
:
Description of the Pins :
• Pin 1 to Pin 8 (Port 1) – Pin 1 to Pin 8 are assigned to Port 1 for simple I/O
operations. They can be configured as input or output pins depending on the
logic control i.e. if logic zero (0) is applied to the I/O port it will act as an output
pin and if logic one (1) is applied the pin will act as an input pin. These pins are
also referred to as P1.0 to P1.7 (where P1 indicates that it is a pin in port 1 and
the number after ‘.’ tells the pin number i.e. 0 indicates first pin of the port. So,
 P1.0 means first pin of port 1, P1.1 means second pin of the po rt 1 and so on).
These pins are bidirectional pins.
• Pin 9 (RST) – Reset pin. It is an active-high, input pin. Therefore if the RST pin
is high for a minimum of 2 machine cycles, the microcontroller will reset i.e. it
will close and terminate all activities. It is often referred as “power-on-reset” pin
because it is used to reset the microcontroller to it’s initial values when power is
on (high).
• Pin 10 to Pin 17 (Port 3) – Pin 10 to pin 17 are port 3 pins which are also
referred to as P3.0 to P3.7. These pins are similar to port 1 and can be used as
universal input or output pins. These pins are bidirectional pins. These pins also
have some additional functions which are as follows:
• P3.0 (RXD) : 10th pin is RXD (serial data receive pin) which is for
serial input. Through this input signal microcontroller receives data
for serial communication.
• P3.1 (TXD) : 11th pin is TXD (serial data transmit pin) which is
serial output pin. Through this output signal microcontroller transmits
data for serial communication.
• P3.2 and P3.3 (INT0′, INT1′ ) : 12th and 13th pins are for External
Hardware Interrupt 0 and Interrupt 1 respectively. When this interrupt
is activated(i.e. when it is low), 8051 gets interrupted in whatever it is
doing and jumps to the vector value of the interrupt (0003H for INT0
and 0013H for INT1) and starts performing Interrupt Service Routine
(ISR) from that vector location.
• P3.4 and P3.5 (T0 and T1) : 14th and 15th pin are for Timer 0 and
Timer 1 external input. They can be connected with 16 bit
timer/counter.
• P3.6 (WR’) : 16th pin is for external memory write i.e. writing data
to the external memory.
• P3.7 (RD’) : 17th pin is for external memory read i.e. reading data
from external memory.
• Pin 18 and Pin 19 (XTAL2 And XTAL1) – These pins are connected to an
external oscillator which is generally a quartz crystal oscillator. They are used to
provide an external clock frequency of 4MHz to 30MHz.
• Pin 20 (GND) – This pin is connected to the ground. It has to be provided with
0V power supply. Hence it is connected to the negative terminal of the power
supply.
• Pin 21 to Pin 28 (Port 2) – Pin 21 to pin 28 are port 2 pins also referred to as
P2.0 to P2.7. When additional external memory is interfaced with the 8051
microcontroller, pins of port 2 act as higher-order address bytes. These pins are
bidirectional.
• Pin 29 (PSEN) – PSEN stands for Program Store Enable. It is output, active-low
pin. This is used to read external memory. In 8031 based system where external
ROM holds the program code, this pin is connected to the OE pin of the ROM.
• Pin 30 (ALE/ PROG) – ALE stands for Address Latch Enable. It is input,
active-high pin. This pin is used to distinguish between memory chips when
multiple memory chips are used. It is also used to de-multiplex the multiplexed
address and data signals available at port 0. During flash programming i.e.
Programming of EPROM, this pin acts as program pulse input (PROG).
• Pin 31 (EA/ VPP) – EA stands for External Access input. It is used to
enable/disable external memory interfacing. In 8051, EA is connected to Vcc as
it comes with on-chip ROM to store programs. For other family members such
as 8031 and 8032 in which there is no on-chip ROM, the EA pin is connected to
the GND.
 • Pin 32 to Pin 39 (Port 0) – Pin 32 to pin 39 are port 0 pins also referred to as
P0.0 to P0.7. They are bidirectional input/output pins. They don’t have any
internal pull-ups. Hence, 10 K? pull-up registers are used as external pull-ups.
Port 0 is also designated as AD0-AD7 because 8051 multiplexes address and
data through port 0 to save pins.
• Pin 40 (VCC) – This pin provides power supply voltage i.e. +5 Volts to the
circuit.
The pin diagram of the 8051 microcontroller is as follows:
1. VCC: This pin is connected to the power supply and provides a voltage of +5V
to the microcontroller.
2. GND: This pin is connected to the ground and serves as the reference voltage
for the microcontroller.
3. XTAL1 and XTAL2: These pins are used for connecting an external crystal
oscillator that provides the clock signal for the microcontroller.
4. Reset: This pin is used for resetting the microcontroller. A high pulse on this pin
resets the microcontroller to its initial state.
5. Port 1: This is an 8-bit bidirectional input/output port that can be used for
interfacing with external devices.
6. Port 2: This is an 8-bit bidirectional input/output port that can be used for
interfacing with external devices.
7. Port 3: This is an 8-bit bidirectional input/output port that can be used for
interfacing with external devices.
8. Port 4: This is an 8-bit bidirectional input/output port that can be used for
interfacing with external devices.
9. INT0: This is an external interrupt 0 input pin.
10. INT1: This is an external interrupt 1 input pin.
11. T0: This is an external timer 0 input pin.
12. T1: This is an external timer 1 input pin.
13. WR: This is the write signal for external memory.
14. RD: This is the read signal for external memory.
15. ALE: This is the address latch enable signal that is used to latch the address for
external memory.
16. PSEN: This is the program store enable signal that is used for accessing the
program memory.
17. 17-24. Address bus: These pins are used for transmitting the address
information to the external memory.
18. 25-32. Data bus: These pins are used for transmitting the data between the
microcontroller and external memory.
19. RST: This is the output signal that indicates the microcontroller is being reset.
20. EA: This is the external access enable signal that is used for selecting the
program memory.
21. VPP: This pin is used for programming the microcontroller.
22. 36-39. XTAL: These pins are used for connecting an external crystal oscillator.
23. P1.0 (AD0) – P1.7 (AD7): These pins are used for interfacing with external
analog devices.

Q6(b) Draw the internal memory organization of 8051 and also Explain register banks and

stack.
ANS. The internal data memory of 8051 is divided into two groups. These are a set of eight
registers and a scratch pad memory. These eight registers are R0 toR7. The address range 00H
to 07H is used to access the registers, and the rest are scratch pad memory.
8051 Provides four register bank, but only one register bank can be used at any point in time.
To select the register bank, two bits of PSW (Program Status Word) are used.

So the following addressing can be used to select register banks.

Address Range Register Bank

00H to 07H Register Bank 0

08H to 0FH Register Bank 1

10H to 17H Register Bank 2

18H to 1FH Register Bank 3

The concept of four register banks is very useful. For servicing the interrupts, this feature is
very good. The interrupt program can use one bank, and the interrupt Service Subroutine (ISS)
can access another bank for better performance. As there are four banks, so for nested
interrupts these can be used

When all of the register banks are being used, the scratch pad area will be 20H to 7FH. But
from 20H to 2FH (16 bytes or 128 bits) can be used as bit addressable RAM. By using some
simple instructions with 8-bit memory address we can check the bit addressing. For an
example the instruction CLR 6FH, using this instruction it clears the location 6FH. As we
know the8-bit address can locate 256 different locations, but here only128-bits are addressable.
Another section of bit addressable locations is 80H to FFH. The remaining locations (30H to
7EH) of the RAM can be used to store variable data and stack.

Stack Area
The stack area in 8051always can be implemented in the internal data memory. Here the stack
pointer (SP) is an only 8-bit register, because the internal RAM area is only in range 00H to
7FH, and when all register banks are being used, the stack location will be in range 30H to
7FH. So in such a case, the SP will be initialized with 2FH.

The stack pointer SP increases before each PUSH operation and decreases after each pop
instruction.
When the 8051 is reset, the Stack Pointer will point to 07H. It means the location 08H to
7FHcan be used as a stack. We are assuming that the register bank 0 is in use and 20H to 27H
are not like bit-addressable area.

Q7.(a) Discuss the different types of assembler directives of 8051 microcontroller.

ANS. Various assembler directives in 8051 microcontrollers are used during assembly
language programming. Unlike instructions being compiled and written to chip program
memory, directives are commands of assembly language itself and have no influence on the
operation of the microcontroller.
Some of them are obligatory part of every program while some are used only to facilitate or
speed up the operation.
Directives are written in the column reserved for instructions. There is a rule allowing only one
directive per program line.

Microcontroller 8051 Directives

Following Assembler Directives are used in 8051 microcontroller.

ORG (Origin)

The ORG directive is used to specify a location in program memory where the program
following directive is to be placed.
Syntax: ORG ROM-address
Address can be given in either in hex or decimal.
For example:
ORG 100
…
…
ORG 1000h
TABLE …
…
This program starts at location 100. The table containing data is to be stored at location 1024
(1000h).

EQU

The EQU directive is used to replace a number by a symbol.

Syntax: Name EQU Constant
For example: MAXIMUM EQU 99
After using this directive, every appearance of the label “MAXIMUM” in the program will
be interpreted by the assembler as the number 99 (MAXIMUM = 99).
Symbols may be defined this way only once in the program. The EQU directive is mostly
used at the beginning of the program therefore.

SET

The SET directive is also used to replace a number by a symbol. The significant difference
compared to the EQU directive is that the SET directive can be used an unlimited number of
times.
Syntax: Name SET Constant
SPEED SET 45
SPEED SET 46
SPEED SET 57

BIT

The BIT directive is used to replace a bit address by a symbol. The bit address must be in the
range of 0 to 255 (00 H to FF H).
Syntax: Name BIT 8051-bit
For example:
TRANSMIT BIT PSW.7 ; Transmit bit (the seventh bit in PSW register); is
assigned the name “TRANSMIT”.
OUTPUT BIT 6 ; Bit at address 06 is assigned the name “OUTPUT”.
RELAY BIT 81 ; Bit at address 81 (Port 0) is assigned the name “RELAY”.

CODE

The CODE directive is used to assign a symbol to a program memory address. Since the
maximum capacity of program memory is 64K, the address must be in the range of 0 to
65535(0000 H to FFFF H).
Syntax: Name CODE code-address
For example:
RESET CODE 0 ; Memory location 00h called “RESET”.
TABLE CODE 1024 ; Memory location 1024h called “TABLE”.

DATA

The DATA directive is used to assign a symbol to an address within internal RAM and SFR.
The address must be in the range of 0 to 255 (00 H to FF H). It is possible to change or assign
a new name to any register.
Syntax: Name DATA data-address
For example:
TEMP12 DATA 32 ; Register at address 32 is named as “TEMP12”.
STATUS_R DATA D0h ; PSW register is assigned the name “STATUS_R”.

IDATA

The IDATA directive is used to change or assign a new name to an indirectly addressed
register. It is an address of entire internal RAM.
Syntax: Name IDATA idata-address
For example:
TEMP22 IDATA 32 ; Register whose address is in register ;at address
32 is named as “TEMP22”
TEMP33 IDATA T_ADR ; Register whose address is in register T_ADR
is named as “TEMP33”.

XDATA

The XDATA directive is used to assign a name to registers within external (additional) RAM
memory. The addresses of these registers cannot be larger than 65535 (0000 h to FFFF h).
Syntax: Name XDATA xdata-address
For example:
TABLE_1 XDATA 2048 ; Register stored in external; memory at
address 2048 is named; as “TABLE_1”.

USING

The USING directive is used to define which register bank (registers R0 -R7) is to be used in
the program.
Syntax: USING Bank-no.
USING 0 ; Bank 0 is used (registers R0-R7 at RAM-addresses 0-7)
USING 1 ; Bank 1 is used (registers R0-R7 at RAM-addresses 8-15)
USING 2 ; Bank 2 is used (registers R0-R7 at RAM-addresses 16-23)
USING 3 ; Bank 3 is used (registers R0-R7 at RAM-addresses 24-31).

END

The END directive is used at the end of every program. It indicates the end of program. The
assembler will stop compiling once the program encounters this directive.
Syntax: END
For example:
END ; End of program

DB (Define Byte)

The DB directive is used for writing specified value into program memory. If several values
are specified, then they are separated by a comma. Here data can be in decimal, binary, hex
or ASCII formats.
If ASCII array is specified, it should be enclosed within single quotation marks. This
directive can be used only if the CSEG segment is active.
DB directive is the only directive that can be used to define ASCII strings larger than two
characters; therefore, it should be used for all ASCII data definitions.
For example:
NUM1 DB 22,33, ‘Alarm’, 44
String_U DB ‘DBATU’
If this directive is preceded by a label, then the label will point to the first element of the
array. It is the number 22 in this example 1.

Q7 (b) What is the difference between PIC and ARM processor? Explain their application
areas.
Difference between PIC and ARM :
S.No. PIC ARM

PIC micro-controller refers to ARM micro-controller refers to

01. Peripheral Interface Controller. Advanced RISC Machine.

PIC micro-controllers are available ARM micro-controllers are available in

02. in 8-bit, 16-bit and 32-bit. 32-bit mostly also available in 64-bit.

It supports PIC, UART, USART, It supports UART, USART, SPI, CAN,

CAN, LIN, Ethernet, SPI, I2S LIN, I2C, Ethernet, I2S, DSP, SAI
03. communication protocol. communication protocol.

It has an effective instruction rate of It has an effective instruction rate of 1

04. 4 clock cycles per instruction. clock cycles per instruction.

It uses Flash, SDRAM, EEPROM

05. It uses SRAM, Flash memory. memory.

It is based on RISC instruction set

06. It is based on some feature of RISC. architecture.
It is based on Harvard memory It is based on modified Harvard
07. architecture. architecture.
PIC micro-controller family includes ARM micro-controller family includes
08. PIC16, PIC17, PIC18, PIC24, PIC32. ARMv4, 5, 6, 7 and series.
It has a very good community
09. support. It has a vast community support.

Its manufacturers are Apple, Nvidia,

Qualcomm, Samsung Electronics, and
10. Its manufacturer is Microchip. TI etc.

It is available with an average cost as It is available with a low cost as

11. compared to the features. compared to the features.

Popular micro-controllers include Popular micro-controllers include

PIC18fXX8, PIC16f88X, LPC2148, ARM Cortex-M0 to ARM
12. PIC32MXX. Cortex-M7, etc.