Laboratory Report Cover Sheet

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

Faculty of Engineering and Technology
Department of Electronics and Communication Engineering
15EC302J VLSI Design
VI Semester, 2020-2021 (Even Semester)

Name : Yash Agarwal

Register No. :RA1811004010158

Title of Experiment : Realization of Multiplier-1

Date of Submission :03/04/2021

Marks
Particulars Max. Marks
Obtained
Pre-Lab and Post Lab 10
Design, HDL Code, In-
15
Lab Performance
Output verification
10
&viva
Lab Report 05

Total 40

REPORT VERIFICATION

Staff Name :

Signature :
 Lab Experiment #6

Realization of Multiplier-1
6.1 Objective: To design and simulate the Braun array multiplier in Verilog and synthesize using EDA
tools

6.2 Software tools Requirement

Equipment’s:
Computer with Xilinx and Modelsim Software Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Software’s: Synthesis tool: Xilinx ISE
Simulation tool: Modelsim Simulator

6.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)

1. What is called Booth recoding?

2. Give the booths recoding transformation of the following number 01111001(0).
3. Give the difference between Booth’s recoding and modified booth’s recoding?
6.4 Problem: Write a Verilog code to implement the 4-bit Braun Array multipliers using structural model.

Verilog Code module braunarray(p,a,b);

output [7:0]p;
input [3:0]a,b;
wire [16:1]w;
wire [12:1]s,c;
and a1(w[1],a[0],b[0]);
and a2(w[2],a[1],b[0]);
and a3(w[3],a[2],b[0]);
and a4(w[4],a[3],b[0]);
and a5(w[5],a[0],b[1]);
and a6(w[6],a[1],b[1]);
and a7(w[7],a[2],b[1]);
and a8(w[8],a[3],b[1]);
and a9(w[9],a[0],b[2]);
and a10(w[10],a[1],b[2]);
and a11(w[11],a[2],b[2]);
and a12(w[12],a[3],b[2]);
and a13(w[13],a[0],b[3]);
and a14(w[14],a[1],b[3]);
and a15(w[15],a[2],b[3]);
and a16(w[16],a[3],b[3]);
fa_st fa1(s[1],c[1],w[5],0,w[2]);
fa_st fa2(s[2],c[2],w[6],0,w[3]);
fa_st fa3(s[3],c[3],w[7],0,w[4]);
fa_st fa4(s[4],c[4],w[9],c[1],s[2]);
fa_st fa5(s[5],c[5],w[10],c[2],s[3]);
fa_st fa6(s[6],c[6],w[11],c[3],w[8]);
fa_st fa7(s[7],c[7],w[13],c[4],s[5]);
fa_st fa8(s[8],c[8],w[14],c[5],s[6]);
fa_st fa9(s[9],c[9],w[15],c[6],w[12]);
fa_st fa10(s[10],c[10],c[7],0,s[8]);
fa_st fa11(s[11],c[11],c[8],c[10],s[9]);
fa_st fa12(s[12],c[12],c[11],c[9],w[16]);
assign p[0]=w[1],
p[1]=s[1],
p[2]=s[4],
p[3]=s[7],
p[4]=s[10],
p[5]=s[11],
p[6]=s[12],
p[7]=c[12];
endmodule

Simulation waveforms:

// TEST BENCH
module braunarray_tb_v;

// Inputs
reg [3:0] a;
reg [3:0] b;
 // Outputs
wire [7:0] p;

// Instantiate the Unit Under Test (UUT)

braunarray uut (
.p(p),
.a(a),
.b(b)
);

initial begin
// Initialize Inputs
a = 15; b = 15; #100;

// Add stimulus here

end

endmodule

Simulation waveforms (Observation) :

Logic Diagram

Fig 6.1 4-bit Braun Array multiplier

6.5 Post Lab:

1. Write the booth multiplier code in Verilog and implement using EDA tools.

A) module BOOTH(X, Y, Z);

input signed [3:0] X, Y;

output signed [7:0] Z;

reg signed [7:0] Z;

reg [1:0] temp;

integer i;

reg E1;

reg [3:0] Y1;

always @ (X, Y)

begin

Z = 8'd0;

E1 = 1'd0;

for (i = 0; i < 4; i = i + 1)

begin

temp = {X[i], E1};

 Y1 = - Y;

case (temp)

2'd2 : Z [7 : 4] = Z [7 : 4] + Y1;

2'd1 : Z [7 : 4] = Z [7 : 4] + Y;

default : begin end

endcase

Z = Z >> 1;

Z[7] = Z[6];

E1 = X[i];

end

if (Y == 4'd8)

begin

Z = - Z;

end

end

endmodule

TEST BENCH :

module BOOTHTP_v;

// Inputs

reg [3:0] X;

reg [3:0] Y;

// Outputs

wire [7:0] Z;

// Instantiate the Unit Under Test (UUT)

BOOTH uut (

.X(X),

.Y(Y),

.Z(Z)

);

initial begin

// Initialize Inputs

X = 0;

Y = 0;

// Wait 100 ns for global reset to finish

#100;

X=-5;
 Y=7;

// Add stimulus here

end

endmodule

Stimulation wave form (post lab answer):

6.6 Result: Therefore ,4-bit braun array multiplier was performed using structural model and testbench.
 Laboratory Report Cover Sheet

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

Faculty of Engineering and Technology

Department of Electronics and Communication Engineering

15EC302J VLSI Design

VI Semester, 2020-2021 (Even Semester)

Name : Yash Agarwal

Register No. :RA1811004010158

Title of Experiment : Realization of Multiplier-II

Date of Submission :03/04/2021

Marks Ob-
Particulars Max. Marks
tained

Pre-Lab and Post Lab 10

Design, HDL Code, In-

15
Lab Performance

Output verification
10
&viva

Lab Report 05

Total 40

REPORT VERIFICATION

Staff Name :

Signature :
Lab Experiment #7 Realization of Multiplier-II

7.1 Objective: To design and simulate the Wallace tree multiplier in Verilog and synthesize using EDA tools

7.2 Software tools Requirement

Equipment’s:

Computer with Xilinx and Modelsim Software Specifications:

HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Software’s: Synthesis tool: Xilinx ISE Simulation tool: Modelsim Simulator

7.3 Prelab Questions

(write pre lab Q & A in an A4 sheet)

1. How carry save multiplier differs from array multiplier?
2. Why the partial sum adders are arranged in tree like fashion?
7.4 Problem: Write a Verilog code to implement the 4-bit Wallace tree multipliers using structural model.

Logic Diagram:

Fig . 7.1 4-bit Wallace tree multiplier

Source code:

module wallace_tree_mul(a, b, z); input [3:0] a;

input [3:0] b;
output [7:0] z;
wire [32:0] w;

and g1 (z[0] , a[0], b[0]);

and g2 (w[27], a[0], b[1]);
and g3 (w[0] , a[1], b[0]);
and g4 (w[1] , a[2], b[0]);
and g5 (w[2] , a[0], b[2]);
and g6 (w[3] , a[1], b[1]);
and g7 (w[4] , a[1], b[1]);
and g8 (w[5] , a[3], b[0]);
and g9 (w[6] , a[0], b[3]);
and g10(w[7] , a[1], b[2]);
and g11(w[8] , a[3], b[1]);
and g12(w[9] , a[1], b[3]);
and g13(w[10], a[2], b[2]);
and g14(w[11], a[2], b[3]);
and g15(w[12], a[3], b[2]);
and g16(w[13], a[3], b[3]);
halfadder h0(w[16], w[17], w[10], w[9]);
halfadder h1(w[14], w[15], w[7], w[6]);
halfadder h2(z[1] , w[28], w[27], w[0]);
FA f0(w[19] , w[20] , w[2] , w[3] , 1'b0);
FA f1(w[21] , w[22] , w[4] , w[5] , w[14]);
FA f2(w[23] , w[24] , w[15] , w[8] , w[15]);
FA f3(w[25] , w[26] , w[17] , w[11] , w[12]);
FA f4(z[2] , w[29] , w[0] , w[1] , w[28]);
 FA f5(z[3] , w[30] , w[20] , w[21] , w[29]);
FA f6(z[4] , w[31] , w[22] , w[23] , w[30]);
FA f7(z[5] , w[32] , w[24] , w[25] , w[31]);
FA f8(z[6] , z[7] , w[26] , w[13] , w[32]);
endmodule

module halfadder(sum,cry,a,b); input a,b;

output sum,cry;

assign sum=a^b; assign

cry=a&b; endmodule

module FA(s,cry,a,b,c); input a,b,c;

output s,cry; assign
s=a^b^c;
assign cry=((a&b)|(b&c)|(c&a)); endmodule.

Simulation waveforms:

// TEST BENCH

module wallace_tree_mul_tb_v;

// Inputs reg [3:0] a;

reg [3:0] b;

// Outputs wire [7:0] z;

// Instantiate the Unit Under Test (UUT) wallace_tree_mul uut (

.a(a),

.b(b),

.z(z)

);

initial begin

// Initialize Inputs a = 0;

b = 0;

// Wait 100 ns for global reset to finish #100; a=1101; b=1001;

// Add stimulus here

end endmodule

Simulation waveforms:
7.5 Post Lab:

1. Write the verilog code for 4-bit Baughly multiplier in structural modeling and implement using EDA tools.

Source code

module ba_multi(a, b, p); input [3:0] a;

input [3:0] b;

output [7:0] p;

wire w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17, w18, w19,w20,w21,w22,w23,w24,w25,w26,w27,w28,w29;

and g0 (w0, a[3], b[0]);

and g1 (w1, a[2], b[0]);

and g2 (w2, a[1], b[0]);

and g3 (p[0],a[0], b[0]);

and g4 (w6, a[3], b[1]);

and g5 (w3, a[2], b[1]);

and g6 (w4, a[1], b[1]);

and g7 (w5, a[0], b[1]);

and g8 (w12, a[3], b[2]);

and g9 (w13, a[2], b[2]);

and g10(w14, a[1], b[2]);

and g11(w15, a[0], b[2]);

and g12(w21, a[3], b[3]);

and g13(w22, a[2], b[3]);

and g14(w23, a[1], b[3]);

and g15(w24, a[0], b[3]);

 fa_df f0 (w8 , w7 , w0 , w3 , 1'b0);

fa_df f1 (w10 , w9 , w1 , w4 , 1'b0); fa_df f2 (p[1], w11 , w2 ,

w5 , 1'b0); fa_df f3 (w17 , w16 , w6 , w13, w7); fa_df f4 (w19 ,

w18 , w8 , w14, w9); fa_df f5 (p[2], w20 , w10, w15, w11);

fa_df f6 (w26 , w25 , w12, w22, w16); fa_df f7 (w28 , w27 ,

w17, w23, w18); fa_df f8 (p[3], w29 , w19, w24, w20); fa_df f9

(p[6], p[7], w21, w25, w31); fa_df f10(p[5], w31 , w26, w27,

w30); fa_df f11(p[4], w30 , w28, w29, 1'b0); endmodule

module fa_df(output s,output cout,input a,input b,input cin); wire z1,z2,z3;

xor(z1,a,b);

xor(s,z1,cin);

and(z2,z1,cin);

and(z3,a,b);

or(cout,z2,z3); endmodule

Test Bench

module multi_tb_v;

// Inputs reg [3:0] a;

reg [3:0] b;

// Outputs wire [7:0] p;

// Instantiate the Unit Under Test (UUT) ba_multi uut(a(a),.b(b),.p(p));

initial begin

// Initialize Inputs a = 0;

b = 0;

// Wait 100 ns for global reset to finish #100;

a=4'b0001; b=4'b0010;
#100; a=4'b0011; b=4'b0001;

#100; a=4'b0100; b=4'b0010;

#100; a=4'b0010; b=4'b0100;

// Add stimulus here

end

endmodule

Simulation Waveform (POST LAB);