Unit 2

18CSC203J-Computer Organization and

Architecture
 Course Outcome
• CLR-2:Analyze the functions of arithmetic
units like adders, multipliers etc.

• CLR-6:Simulate simple fundamental units like

half adder, full adder etc.

• CLO-2:Apply Boolean algebra as related in

designing computer logic through simple
combinational and sequential logic circuits
 Table of Contents
 Addition and subtraction of signed numbers
 Design of fast adders – Ripple Carry Adder and Carry
Look ahead Adder
 Multiplication of positive numbers
 Signed operand multiplication
 Fast multiplication - Bit pair recoding of Multipliers
 Carry Save Addition of Summands
 Integer division – Restoring Division and Non Restoring
Division
 Floating point numbers and operations
Integer Representation
 Only have 0 & 1 to represent everything
 Positive numbers stored in binary
 e.g. 41=00101001
 No minus sign
 No period
 Sign-Magnitude
 One's Complement
 Two’s compliment
• In integer
• MSB-Most significant Bit
• LSB-Least Significant Bit

If MSB is 0 then the integer is +ve number

MSB is 1 then the integer is –ve number
The value of bits in signed and unsigned binary numbers

  Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unsigned 27 = 128 26 = 64 25 = 32 24= 16 23= 8 22 = 4 21 = 2 20 = 1

Signed -(27) = -128 26 = 64 25 = 32 24 = 16 23 = 8 22 = 4 21= 2 20 = 1
Integer Representation (cont’d)
Sign Magnitude: One's Complement Two's Complement
000 = +0 000 = +0 000 = +0
001 = +1 001 = +1 001 = +1
010 = +2 010 = +2 010 = +2
011 = +3 011 = +3 011 = +3
100 = -0 100 = -3 100 = -4
101 = -1 101 = -2 101 = -3
110 = -2 110 = -1 110 = -2
111 = -3 111 = -0 111 = -1

Issues: balance, number of zeros, ease of operations

Which one is best? Why?
 SUMMARY OF THE TABLE

 SIGN & MAGNITUE SYSTEM: Negative value

is obtained by changing the sign bit (MSB)
 SIGNED 1’S COMPLEMENT: Negative number
is obtained by complementing each bit of the
corresponding positive number i.e (2n-1) –N
 SIGNED 2’S COMPLEMENT: Negative number
is obtained by taking 2’s complement of positive
number
2 n-N
Range: - (2n-1) to + (2n-1-1)
 Binary Subtraction

• Subtraction and Borrow, these two words will be

used very frequently for the binary subtraction.
There four rules of the binary subtraction.
 Binary Multiplication
• Binary multiplication is similar to decimal
multiplication. It is simpler than decimal
multiplication because only 0s and 1s are
involved. There four rules of the binary
multiplication.
 Binary Division
• Binary division is similar to decimal division. It is
called as the long division procedure
 Half Adder
• Half adder is a combinational logic circuit with
two input and two output. The half adder circuit is
designed to add two single bit binary number A
and B. It is the basic building block for addition
of two single bit numbers. This circuit has two
outputs carry and sum.
Truth Table and Circuit Diagram

Boolean Expression
 Full Adder
• Full adder is developed to overcome the drawback
of Half Adder circuit. It can add two one-bit
numbers A and B, and carry c. The full adder is a
three input and two output combinational circuit.
Truth Table and Circuit Diagram
 Half Subtractor
• Half subtractor is a combination circuit with two
inputs and two outputs (difference and borrow). It
produces the difference between the two binary bits at
the input and also produces a output (Borrow) to
indicate if a 1 has been borrowed. In the subtraction
(A-B), A is called as Minuend bit and B is called as
Subtrahend bit.
 Truth Table and Circuit Diagram

From the truth table, Boolean Expression can be derived as:

D = A’B + AB’ =  A ⊕ B
Bo = A’B
Half Subtractors
 Full Subtractor
• The disadvantage of a half subtractor is overcome by
full subtractor. The full subtractor is a combinational
circuit with three inputs A, B, Bin and two output D
and Bo. A is the minuend, B is subtrahend, Bin is the
borrow produced by the previous stage, D is the
difference output and Bo is the borrow output.
 Half Subtractor
Half Subtractor
 Ripple Carry Adder
Typical Ripple Carry Addition is a Serial Process:
• Addition starts by adding LSBs of the augend and addend.
• Then next position bits of augend and addend are added
along with the carry (if any) from the preceding bit.
• This process is repeated until the addition of MSBs is
completed.
• Speed of a ripple adder is limited due to carry propagation or
carry ripple.
• Sum of MSB depends on the carry generated by LSB.
 Ripple Carry Adder
Example: 4-bit Carry Ripple Adder
• Assume to add two operands A and B where
A = A3 A2 A1 A0
B = B3 B2 B1 B0
A= 1 0 1 1 +
B= 1 1 0 1
--------------------
A+B=1 1 0 0 0
Cout S3 S2 S1 S0
 Ripple Carry Adder
Carry Propagation
• From the above example it can be seen that we are
adding 3 bits at a time sequentially until all bits are
added.
• A full adder is a combinational circuit that performs
the arithmetic sum of three input bits: augends Ai,
addend Bi and carry in Cin from the previous adder.
• Its result contain the sum Si and the carry out, Cout
to the next stage.
example
 Ripple Carry Adder
4-bit Adder
• A 4-bit adder circuit can be designed by first designing the 1-
bit full adder and then connecting the four 1-bit full adders to
get the 4-bit adder as shown in the diagram above.
• For the 1-bit full adder, the design begins by drawing the
Truth Table for the three input and the corresponding output
SUM and CARRY.
• The Boolean Expression describing the binary adder circuit
is then deduced.
• The binary full adder is a three input combinational circuit
which satisfies the truth table given below.
 Ripple Carry Adder
Full Adder
 Ripple Carry Adder
4-bit Adder
Design of Fast adder:
Carry Look-ahead Adder
• A carry-look ahead adders (CLA) is a type
of adder used in digital logic. A carry-look ahead
adder improves speed by reducing the amount of
time required to determine carry bits.
• It can be contrasted with the simpler, but usually
slower, ripple carry adder for which the carry bit
is calculated alongside the sum bit, and each bit
must wait until the previous carry has been
calculated to begin calculating its own result and
carry bits (see adder for detail on ripple carry
adders)
• The carry-look ahead adder calculates one or
more carry bits before the sum, which reduces the
wait time to calculate the result of the larger value
bits.
• In a ripple adder the delay of each adder is 10 ns ,
then for 4 adders the delay will be 40 ns.
• To overcome this delay Carry Look-ahead Adder
is used.
Carry Look-ahead Adder
• Different logic design approaches have been employed
to overcome the carry propagation delay problem of
adders.
• One widely used approach employs the principle of
carry look-ahead solves this problem by calculating the
carry signals in advance, based on the input signals.
• This type of adder circuit is called as carry look-ahead
adder (CLA adder). A carry signal will be generated in
two cases:
(1) when both bits Ai and Bi are 1, or
(2) when one of the two bits is 1 and the carry-in (carry
of the previous stage) is 1.
Carry Look-ahead Adder
The Figure shows the full adder circuit used to
add the operand bits in the Ith column; namely
Ai & Bi and the carry bit coming from the
previous column (Ci ).
Carry Look-ahead Adder
In this circuit, the 2 internal signals Pi and Gi
are given by:

The output sum and carry can be defined as

Carry Look-ahead Adder
• Gi is known as the carry Generate signal since a carry
(Ci+1) is generated whenever Gi =1, regardless of the
input carry (Ci).
• Pi is known as the carry propagate signal since whenever
Pi =1, the input carry is propagated to the output carry,
i.e., Ci+1. = Ci (note that whenever Pi =1, Gi =0).
• Computing the values of Pi and Gi only depend on the
input operand bits (Ai & Bi) as clear from the Figure and
equations.
• Thus, these signals settle to their steady-state value after
the propagation through their respective gates.
Carry Look-ahead Adder
• Computed values of all the Pi’s are valid one XOR-gate
delay after the operands A and B are made valid.
• Computed values of all the Gi’s are valid one AND-gate
delay after the operands A and B are made valid.
• The Boolean expression of the carry outputs of various
stages can be written as follows:
Carry Look-ahead Adder
Carry Ci+1 = XiYi + YiCi + CiXi
= XiYi + Ci (Xi +Yi)
= Gi + CiPi. (Generate Carry + Ci * Propagate Carry)

Carry Ci+1 = Gi + CiPi

i.e. Ci = (Gi-1 + Pi-1Ci-1) &
Ci-1 = (Gi-2 + Pi-2Ci-2).
Carry Look-ahead Adder
• Ci+1 = Gi + CiPi.

always, except when Xi

= 1 & Yi = 1. But, then Gi = 1to make Ci+1
= 1; hence Bit cell
Carry Look-ahead Adder
• In general C i+1 = G i + PiG i-1 + PiP i-1 G i-2 + … + Pi P i-1 ……….P 1G0 + Pi P i-1 … P0G0.
• Ci+1-- in 3 Gates delay; Si – in 4 Gates delay irrespective of n. C1 in 3 gates delay,C2 in 3 gates
delay,C3 in 3 gates delay and so on.
• S0 in 4 gates delay, S1 in 4 gates delay, S2 in 4 gates delay and so on.
Carry Look-ahead Adder
Implementing these
expressions (for a 4-
bit adder), results in
the logic diagram.
(IC- 74182)
4-bit Carry Look-ahead Adder
4-bit Carry Look-ahead Adder
• independent of n,
• the n-bit addition process requires only four
gate delays (against 2n)
• increasing ‘n’ increases gate fan-in
requirements (C 4 – fan_in = 5)
• Longer version adders - cascading
 Binary Multiplier
• Multiplication of binary numbers is performed in the same way
as with decimal numbers. The multiplicand is multiplied by
each bit of the multiplier, starting from the least significant bit.
• The result of each such multiplication forms a partial product.
Successive partial products are shifted one bit to the left.
• The product is obtained by adding these shifted partial
products.
• Example 1: Consider multiplication of two numbers, say A and
B (2 bits each),
• C = A x B.
 Binary Multiplier
• Unsigned number multiplication
• two n-bit numbers; 2n-bit result
 Binary Multiplier
• The first partial product is formed by multiplying the
B1B0 by A0. The multiplication of two bits such as
A0 and B0 produces a 1 if both bits are 1; otherwise it
produces a 0 like an AND operation. So the partial
products can be implemented with AND gates.
• The second partial product is formed by multiplying
the B1B0 by A1 and is shifted one position to the left.
• The two partial products are added with two half
adders (HA). Usually there are more bits in the partial
products, and then it will be necessary to use FAs.
Binary Multiplier
 Binary Multiplier
• The least significant bit of the product does not have
to go through an adder, since it is formed by the
output of the first AND gate as shown in the Figure.
 Shift-and-Add Multiplier
• Shift-and-add multiplication is similar to the
multiplication performed by paper and pencil.
• This method adds the multiplicand X to itself Y
times, where Y denotes the multiplier.
• To multiply two numbers by paper and pencil, the
algorithm is to take the digits of the multiplier one at
a time from right to left, multiplying the multiplicand
by a single digit of the multiplier and placing the
intermediate product in the appropriate positions to
the left of the earlier results.
 Shift-and-Add Multiplier
• As an example, consider the multiplication of two
unsigned 4-bit numbers,
• 8 (1000) and 9 (1001).
 Shift-and-Add Multiplier
• In the case of binary multiplication, since the digits
are 0 and 1, each step of the multiplication is simple.
• If the multiplier digit is 1, a copy of the multiplicand
(1 ×multiplicand) is placed in the proper positions;
• If the multiplier digit is 0, a number of 0 digits (0 ×
multiplicand) are placed in the proper positions.
• Consider the multiplication of positive numbers. The
first version of the multiplier circuit, which
implements the shift-and-add multiplication method
for two n-bit numbers, is shown in Figure.
Shift - and - Add multiplier
 Shift-and-Add Multiplier
• For Example, Perform the multiplication 9 x 12
(1001 x 1100). Finally, both A and Q contains the
result of product.
 Shift-and-Add Multiplier
Example 2:
• A = 0000 M ( Multiplicand)  13 ( 1 1 0 1)
Q(Multiplier)  11 (1 0 1 1).
Signed Multiplication - Booth Algorithm
• A powerful algorithm for signed number
multiplication is Booth’s algorithm which generates a
2n bit product and treats both positive and negative
numbers uniformly.
• This algorithm suggest that we can reduce the number
of operations required for multiplication by
representing multiplier as a difference between two
numbers.
Signed Multiplication - Booth Algorithm
• A powerful algorithm for signed number
multiplication is Booth’s algorithm which generates a
2n bit product and treats both positive and negative
numbers uniformly.
• This algorithm suggest that we can reduce the number
of operations required for multiplication by
representing multiplier as a difference between two
numbers.
Signed Multiplication - Booth Algorithm
Signed Multiplication - Booth Algorithm
 FAST MULTIPLICATION

1.BOOTH RECODING OF MULTIPLERS

2.BIT PAIR RECODING OF MULTIPLIERS
3.CARRY SAVE ADDITION OF SUMMANDS
 The BOOTH RECODED MULTIPLIER
• Booth multiplication reduces the number of
additions for intermediate results, but can
sometimes make it worse as we will see.
• Booth multiplier recoding table
 The BOOTH RECODED MULTIPLIER
• Booth Recoding:
(i) 3010 : 0 1 1 1 1 00
• +1 0 0 0 -1 0
• (ii) 10010: 0 1 1 0 0 1 0 0 0
•
• +1 0 -1 0 +1 -1 0 0
• (iii) 98510: 0 0 1 1 1 1 0 1 1 0 0 1 0
• 0 +1 0 0 0 -1 +1 0 -1 0 +1 -1
 BOOTH Algorithm
Booth algorithm treats both +ve &
-ve operands equally.
(a) + Md X + Mr
 BOOTH Algorithm
Booth algorithm treats both +ve &
-ve operands equally.
(b) - Md X + Mr
 BOOTH Algorithm
Booth algorithm treats both +ve &
-ve operands equally.
(c) + Md X - Mr
 BOOTH Algorithm
Booth algorithm treats both +ve &
-ve operands equally.
(d) - Md X - Mr
BOOTH Algorithm
 Fast Multiplication
• There are two techniques for speeding up the
multiplication operation.
• The first technique guarantees that the
maximum number of summands (versions of
the multiplicand) that must be added is n/2
for n-bit operands.
• The second technique reduces the time
needed to add the summands (carry-save
addition of summands method).
 Bit-Pair Recoding of Multipliers
• This bit-pair recoding technique halves the maximum
number of summands. It is derived from the Booth
algorithm.
• Group the Booth-recoded multiplier bits in pairs, and
observe the following: The pair (+1 -1) is equivalent to the
pair (0 +1).
• That is, instead of adding —1 times the multiplicand M at
shift position i to + 1 x M at position i + 1, the same result
is obtained by adding +1 x M at position I Other examples
are: (+1 0) is equivalent to (0 +2),(-l +1) is equivalent to (0
—1). and so on
Bit-Pair Recoding of Multipliers
Bit-Pair Recoding of Multipliers
 Carry-Save Addition of Summands

• A carry-save adder is a type of digital adder, used to efficiently compute the sum of
three or more binary numbers.
• A carry-save adder (CSA), or 3-2 adder, is a very fast and cheap adder that does not
propagate carry bits.
• A Carry Save Adder is generally used in binary multiplier, since a binary multiplier
involves addition of more than two binary numbers after multiplication.
• It can be used to speed up addition of the several summands required in
multiplication
• It differs from other digital adders in that it outputs two (or more) numbers, and the
answer of the original summation can be achieved by adding these outputs together.
• A big adder implemented using this technique will usually be much faster than
conventional addition of those numbers.

Fast Multiplication
Bit pair recoding reduces summands by a factor of 2
Summands are reduced by carry save addition
Final product can be generated by using carry look ahead adder
 Carry-Save Addition of Summands

• Disadvantage of the Ripple Carry Adder - Each full adder has to

wait for its carry-in from its previous stage full adder. This
increase propagation time. This causes a delay and makes ripple
carry adder extremely slow. RCAr is very slow when adding
many bits.
• Advantage of the Carry Look ahead Adder - This is an improved
version of the Ripple Carry Adder. Fast parallel adder. It
generates the carry-in of each full adder simultaneously without
causing any delay. So, CLAr is faster (because of reduced
propagation delay) than RCAr.
• Disadvantage the Carry Look-ahead Adder - It is costlier as it
reduces the propagation delay by more complex hardware. It
gets more complicated as the number of bits increases.
Ripple Carry Array
Carry Save Array
 Carry-Save Addition of Summands

• Consider the addition of many summands, We can:

Group the summands in threes and perform carry-save addition
on each of these groups in parallel to generate a set of S and C
vectors in one full-adder delay
Group all of the S and C vectors into threes, and perform carry-
save addition of them, generating a further set of S and C vectors
in one more full-adder delay
Continue with this process until there are only two vectors
remaining
They can be added in a Ripple Carry Adder (RPA) or Carry Look-
ahead Adder (CLA) to produce the desired product
Carry-Save Addition of Summands
Carry-Save Addition of Summands
Carry-Save Addition of Summands
 Integer Division

• More complex than multiplication

• Negative numbers are really bad!
• Based on long division
Integer Division

• Decimal Division
• Binary Division

Figure: Longhand division examples

 Integer Division

Longhand Division operates as follows:

• Position the divisor appropriately with respect to the dividend
and performs a subtraction.
• If the remainder is zero or positive, a quotient bit of 1 is
determined, the remainder is extended by another bit of the
dividend, the divisor is repositioned, and another subtraction is
performed.
• If the remainder is negative, a quotient bit of 0 is determined,
the dividend is restored by adding back the divisor, and the
divisor is repositioned for another subtraction
 Restoring Division
• Similar to multiplication circuit
• An n-bit positive divisor is loaded into register M and an n-bit
positive dividend is loaded into register Q at the start of the
operation.
• Register A is set to 0
• After the division operation is complete, the n-bit quotient is in
register Q and the remainder is in register A.
• The required subtractions are facilitated by using 2’s
complement arithmetic.
• The extra bit position at the left end of both A and M
accommodates the sign bit during subtractions.
Restoring Division

Figure: Logic Circuit arrangement for binary Division (Restoring)

Restoring Division

Figure: Flowchart for Restoring Division

Restoring Division
Restoring Division
 Non-Restoring Division

• Initially Dividend is loaded into register Q,

and n-bit Divisor is loaded into register M
• Let M’ is 2’s complement of M
• Set Register A to 0
• Set count to n
• SHL AQ denotes shift left AQ by one position leaving Q0 blank.
• Similarly, a square symbol in Q0 position denote, it is to be
calculated later
Non-Restoring Division

Figure: Flowchart for Non-Restoring Division

Non-Restoring Division
Non-Restoring Division
Non-Restoring Division
 Floating Point Numbers and Operations
Floating Point Number Representation (FPR)
±Significant x Base±Exponent
Example: +10.55 x 1055

Why FPR?
• Consider a very small number 0.00000000005
• As it consists of many 0’s after the decimal point, it
requires more number bits for representation
• 0.00000000005 is represented as 0.5 x 10-10, it will require only fewer bits
• Consider a very large number 50000000000 which can be represented as
5 x 1010 (+5
• Consider the example 0.123 x 104 = 0.0123 x 105 = 123 x 103
• But we need a fixed and single representation for floating point numbers.
For this normalization is required.
 Floating Point Numbers and Operations
Normalization rules for floating point number
There are 2 rules:
(1)The integer part should be 0 n

(2)0.d1d2...dn x B±E then d1 > 0 and all di ≥ 0

i=2

In the example 0.123 x 10 = 0.0123 x 105 = 123 x 103, the strikethrough representations are wrong with respect to normalization rules.
4

Two floating point representation techniques are,

(3)Single precision (32 bits or 4 bytes)
(4)Double precision (64 bits or 8 bytes)
 Floating Point Numbers and Operations
Single Precision and Double Precision Format
 Floating Point Numbers and Operations
Decimal number into IEEE 754 32-bit floating point number
 Floating Point Numbers and Operations
Floating Point Arithmetic Addition/Subtraction
Steps to add/subtract two floating point numbers:
1. Compare the magnitudes of the exponents and make suitable
alignment to the number with the smaller magnitude of exponent
2. Perform the addition/subtraction
3. Perform normalization by shifting the resulting mantissa and
adjusting the resulting exponent
Example: Add 1.1100 x 24 and 1.1000 x 22
1. Alignment: 1.1000 x 22 has to be aligned to 0.0110 x 24 1.1100
2. Addition: Add the numbers to get 10.0010 x 24 0.0110
3. Normalization: Find normalized result 10.0110
0.1000 x 26 (assuming 4-bits are allowed after
decimal point)
 Floating Point Numbers and Operations
Floating Point Arithmetic Addition/Subtraction
 Reference Links

Ripple Carry Adder

• https://www.gatevidyalay.com/tag/advantages-of-ripple-carry-adder/

Floating Point Numbers and Operations

• https://www.youtube.com/watch?v=XOMTNy2qiZ0&t=72s
• https://www.youtube.com/watch?v=8afbTaA-gOQ
• https://www.youtube.com/watch?v=w7NQTb1FTDU