MODULE 2

1) Design a 2x1 multiplexer using CMOS logic (3) [June 2022]

Scheme: MUX logic function implementation using variables 1 mark realization 2 marks

Here A and B are inputs and S is the select signal. Draw the CMOS inverter itself at vout.,and
also give the truth table.
2) Draw the circuit of a MOS inverter with saturated NMOS load (3) [June 2022]
Scheme: Circuit diagram 3 marks

3) What are the advantages of CMOS logic (3) [ May 2023]

Scheme: Any 3 advantages (3 marks)
CMOS offers
relatively high speed,
low power dissipation,
high noise margins in both states,
will operate over a wide range of source and input voltages

4. What are transmission gates? State the advantages of transmission gates (3) [JAN 2024]
A transmission gate is similar to a relay that can conduct or block in both directions by a control
signal with almost any voltage potential. The transmission gate is mainly a bi-directional switch
enabled by the gate signal 'C'. The control signals to the transmission gate C and C’ are
complementary to each other. When C = 1 both MOSFETs are ON and the signal pass through
the gate i.e. A = B if C = 1. Whereas C = 0 makes the MOSFETs cut off creating an open circuit
between nodes A and B.

Advantages
•They output both strong “1” and strong “0”
•TG consists of 2 transistors in parallel. This reduces the resistance to half that of using a single
pass transistor.
5) Draw and explain a CMOS inverter (3) [Jan 2024]
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and
gate terminals, supply voltage VDD at the PMOS source terminal, ground connected at
the NMOS source terminal, VIN -connected to gate terminals and VOUT connected to
the drain terminals.
 The NMOS transistor has input from Vss (ground) and the PMOS transistor has input
from VDD. When a high voltage (~ VDD) is given at input terminal of the inverter,
the PMOS becomes an open circuit (OFF), and NMOS switched ON so the output will
be pulled down to GND. When a low-level voltage (< VDD, ~0v) applied to the
inverter, the NMOS switched OFF and PMOS switched ON. So the output becomes
VDD.
The circuit topology is complementary push-pull in the sense that for high input, the
nMOStransistor drives (pulls down) the output node while the pMOStransistor acts as
the load, and for low input the pMOStransistor drives (pulls up) the output node while
the nMOStransistor acts as the load. Consequently, both devices contribute equally to
the circuit operation characteristics
Essays:
6b) Implement the 4x1 multiplexer using Transmission gates (4) [June 2022]
Scheme: Implementation using transmission gate (4 marks)
7 a) What is meant by pass transistor logic? What are the differences in transmission
characteristics of NMOS and P MOS transistors? (10) [June 2022]
Scheme: Pass transistor logic explanation (2 marks). Characteristics of NMOS transistors (4
marks) Characteristics of PMOS transistors (4 marks)
Or
b) Explain the working of a pass transistor. (4) [June 2023]
Scheme: Diagram-2 marks, Explain-2 marks
A pass-transistor logic attempts to reduce the number of transistors required to implement the
same logic. It reduces the count of transistors used to make different logic gates, by eliminating
redundant transistors. Transistors are used as switches to pass logic levels between nodes of a
circuit, instead of as switches connected directly to supply voltages. Either NMOS or PMOS
can be used as PTL. The control signal is applied to gate of N-transistor and pass signal applied
to sourceof N-transistor. Basic concept: One input is connected to gate and another input to
source. So when gate is high (ie. TxrON) source signal whether high or low will be passed to
output. It is known as pass txr since it passes logic from i/p node to o/p node.
8a) Describe in detail about pass transistor and transmission gate logic (8) [ May 2023]
Scheme: Pass Transistor logic (4 marks) Transmission gate logic (4 marks)
Refer earlier questions. Give examples.
b) Explain switching power dissipations in CMOS logic (6) [ May 2023]
Scheme: Types (2 marks)explanation (4 marks)
Or
b) What are the factors that affect the static and dynamic power dissipations in a CMOS circuit?
Discuss the total power dissipation with proper equations and derivations. (7) [June 2023]
Scheme: Explain-3 marks, Derivations-4 marks
The current IDD flowing from power supply to ground gives a dissipated power of P= VDD
IDD where VDD = constant. So value of P is found by studying the nature of current flow.
Currents are usually divided into static (or DC) and dynamic (or switching) contributions. Thus
two component that establish the amount of power dissipated in a CMOS circuit.

1. Static dissipation due to leakage current or other current drawn continuously from the power
supply
2. Dynamic dissipation due to a) switching transient current or “short-circuit” current
b) charging and discharging of capacitor
Total Power P = PDC+Pdyn
PDC = static/dc term ; Pdyn = due to dynamic switching events.
Static or DC Power dissipation
When Vinis logic 0 or logic 1, nMOS or pMOS is off respectively and ideally there is no direct
current flow path between VDD and Ground. But in realistic case a small leakage current exists
due to: 1) Sub threshold leakage current –current which flows between drain & source when
input voltage is less than threshold voltage. 2) Gate leakage –when gate oxide is very thin, it
allows the current to pass through it. 3) Junction Leakage –diodes are reverse biased and causes
a small amount of current to flow causing leakage at junctions. All these contribute to the static
dissipation. The leakage current is denoted as IDDQ and is called Quiescent leakage current and
is the order of picoampere per gate.
PDC = VDDIDDQ
Dynamic dissipation
Current is required to charge and discharge the output capacitive load. Consider a square wave
input of time period T and switching frequency f = 1/T Hz. Consider first half cycle, Vin = 0,
Vout =1. pMOS ON, nMOS OFF, Cout charges to VDD through pMOS. During second half
cycle, Vin = 1, Vout =0. pMOS OFF, nMOS ON, Cout discharges to Gnd through nMOS. A
complete cycle effectively creates a path for current to flow from the power supply to ground.

Charging event leaves Cout with a voltage of Vout= VDD. This corresponds to stored electric
charge on capacitor of Qe= CoutVDD Coulombs. During discharge same amount of charge is
lost. Average power dissipated over a single cycle with a period T is Pav= VDD IDD= VDD(Qe/T)
substituting Qe and f = 1/T Hz . Switching power, Psw= CoutV2DDf.
Short circuit dissipation (Psc)
During transition from either 0 to 1 or from 1 to 0, both transistors are ON for a short period of
time. Results in short current pulse from VDD to VSS.
Total dynamic power Pdyn= Psw+ Psc
Total Power = PDC+ Pdyn which will be dominated by the dynamic term.
The dynamic power dissipation is proportional to signal frequency. i.e. A fast circuit dissipates
more power than a slow circuit. If switching speed is doubled, dynamic power dissipation also
doubles.

9a) From the VI characteristics of NMOS and PMOS transistors, how can you graphically
arrive at the VTC of a CMOS inverter? Show the different regions of operation of CMOS
inverter in the VTC.
(10) [June 2023]
Scheme: Diagrams-4 marks, Explain-3 marks, Explain 5 regions of opearation-3 marks
Or
a) Illustrate CMOS inverter DC characteristics with neat diagrams. Explain the different
regions (10) [June 2022]
Scheme: CMOS inverter diagram (1 marks) DC characteristics indicating 5 regions (2 marks)
explanation of each region (7 marks)
Voltage Transfer Characteristic (VTC)
–plot of Vout as a function of Vin
–vary Vin from 0 to VDD
–find Vout at each value of Vin
A

D
E

Region A:
Vin = 0V,
pMOS : ohmic/linear,
nMOS : cut-off
pMOS pulls Vout to VDD
There is no current flow in the circuit.
Vout = Output High Voltage, VOH = VDD
Maximum output voltage occurs when input is low.
Region B:
Vin is increased beyond the threshold voltage of nMOS.
nMOS conducts and has a large voltage between source and drain - saturation
Vin <= VIL
nMOS : Saturation
pMOS still in ohmic/linear state but with
decreased gate drive.
Vout shows a downward transition and > VDD/2 ≈ VOH
A small current flows from VDD supply to Vss ground
Region C:
This is at the middle of the transition curve.
Most of energy consumed in switching from one state to other state attribute
to large current flow in this region.
Here both transistors are in saturation . ie. both ON; IDSp = -IDSn
Vin = VDD/2 = VM = Vout

Region D
Vin >= VIH
nMOS : ohmic /linear
pMOS : Saturation
A small current flows from VDD supply
to Vss ground.
Vout is low and is < VDD/2 ≈ VOL
Region E
Vin = VDD
pMOS is cut-off
nMOS is linear/ohmic
nMOS pulls Vout to Ground
There is no current flow in the circuit.
Vout = Output Low Voltage , VOL = 0 V
Minimum output voltage occurs when input is high.
Region A & E are static conditions.

From the VI characteristics of NMOS and PMOS transistors, how can you graphically
arrive at the VTC of a CMOS inverter
A complementary CMOS inverter is implemented using a series connection of
PMOS and NMOS transistor as shown in Figure below. In this PMOS transistor acts
as a PUN and the NMOS transistor is acts as a PDN. In order to plot the DC transfer
characteristics graphically, I-V characteristics of NMOS and PMOS transistors are
superimposed such graphical representation is called as a load line plot. It requires
that the I-V curves of the NMOS and PMOS devices are transformed onto a
common co-ordinate set.
11 a) Derive the expression for switching threshold of a CMOS inverter. (7) [June 2023][Jan
2024]
Scheme: Derivation-6 marks (May give 2 marks if written what is switching threshold even if
derivation is not complete) Final expression-1 mark
 12a) Why PMOS transistor can pass only strong ones and NMOS can pass strong zeros?(6)
[jan 2024]
b) Implement a 2:1 mux using pass transistor logic and transmission gate logic.(7)[Jan 2024]
or
4) Explain the implementation of a 2:1 multiplexer using transmission gate logic. (3) [June
2023]
Scheme: Diagram-2 marks, Explain-1 mark
The transmission gate is mainly a bi-directional switch enabled by the gate signal 'C'. The
control signals to the transmission gate C and C’ are complementary to each other. When C =
1 both MOSFETs are ON and the signal pass through the gate i.e. A = B if C = 1. Whereas C =
0 makes the MOSFETs cut off creating an open circuit between nodes A and B.

Using PTL,
16) 14a) Realize the logic functions using CMOS logic
(i) X= ((A+B)C.D))’
(ii) Y= (A+(B.C)) ‘ (8) [ Jan 2024]

3 Implement AND function using NMOS logic (3) [ May 2023]

Scheme: Implementation (3 marks)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
3 How can you implement 𝐴(𝐵+𝐶)̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ using static CMOS logic? (3) [June 2023]
Scheme: Diagram – 3 marks

b) Realize the logic function X= ((A+B).(C+D))’ using CMOS logic (4) [June 2022]
Scheme: Implementation of logic function using CMOS logic 4 marks
b) Implement the following using Transmission gates
i) NAND
ii) NOR
iii) XOR (6) [ May 2023]
Scheme: Implementation using transmission gate (2 marks each)
14a) Realize the logic functions using CMOS logic
(i) X= ((A.B)+(C.D))’
(ii) Y= (A.(B+C.D)) (8) [ May 2023]
Scheme: Implementation of logic function using CMOS logic 4 marks each