FPGA Based Design EE-410T

Spring-2023
CLO1 CLO2 CLO3 Total

Comments:

Assignment No: 03 Date of Submission:

April-26-2023
Experiment Title:
Design of Moore/Mealy State Machines for sequence 101011
and 3 1’s
Submitted By:
Sardar Muhammad Ali
Batch: Teacher:
BSEE 20-24 Mr. Muhammad
Shahid Nazir
Semester Section:
6th Electronics

Department of Electrical
Engineering
Contents
Comments:....................................................................................... Error! Bookmark not defined.
1 Objectives: ............................................................................................................................... 3
2 Introduction: ............................................................................................................................. 3
3 Task No.1 (Implementation of 101011):.................................................................................... 3
3.1 Implementation using Mealy State Machine ...................................................................... 3
3.2 State Diagram (Mealy 101011) .......................................................................................... 3
3.3 Mealy Verilog Code (101011) ............................................................................................ 4
3.4 Mealy Results (101011) .................................................................................................... 5
3.4.1 Console View: ................................................................................................................... 5
3.5 Discussion and Conclusion: .............................................................................................. 6
4 Implementation Using Moore State machine ............................................................................ 6
4.1 State Diagram (Moore 101011) ......................................................................................... 6
4.2 Moore Verilog Code (101011) ........................................................................................... 7
4.3 Moore Results ................................................................................................................... 8
4.3.1 Console View .................................................................................................................... 8
4.3.2 Simulation Waveform (Moore 101011): ............................................................................. 8
4.3.3 Discussion and Conclusion: .............................................................................................. 9
5 Task No.2 (Implementation of three 1’s): .................................................................................. 9
5.1 Implementation Using Moore State machine ..................................................................... 9
5.1.1 State Diagram (Moore) ...................................................................................................... 9
5.2 Moore Verilog Code ........................................................................................................ 10
5.3 Moore Results ................................................................................................................. 11
5.3.1 Console View .................................................................................................................. 11
5.3.2 Simulation Waveform (Moore 111): ................................................................................. 11
5.3.3 Discussion and Conclusion: ............................................................................................ 12
6 Implementation Using Mealy State machine ........................................................................... 12
6.1.1 State Diagram (Mealy) ........................................................................................................ 12
6.2 Mealy Verilog Code ......................................................................................................... 13
6.3 Moore Results ................................................................................................................. 14
6.3.1 Console View .................................................................................................................. 14
6.4 Discussion and Conclusion ............................................................................................. 15
7 References:............................................................................................................................ 15
1 Objectives:
 State machine (Moore & Mealy) implementation of bit sequence 101011
 To detect three consecutive zeros (1’s) from a user specified bit-
sequence when input to the device
2 Introduction:
In digital communication systems, when it is important to recognize particular bit sequences
within a data stream, sequence detectors are frequently utilized. The unique needs of the
application and the qualities of the input data determine whether to use an overlapping or
non-overlapping sequence detector. While a non-overlapping sequence detector may be more
appropriate for applications where the target sequence has a fixed location within the input
data, an overlapping sequence detector may be better suited for applications where the target
sequence can occur in multiple locations within the input data.
An output 1 is produced whenever the target sequence has been found by a sequence
detector, which is a sequential state machine that accepts a string of bits as input. A Mealy
machine's output is based on both its current state and an external input (x). As a result, along
with the inputs, the output is printed outside the states in the diagram. Sequence detectors
come in two varieties:
1. Overlapping
2. Non-Overlapping
In a detector for overlapping sequences, the final bit of one sequence becomes the beginning
bit of the following sequence. A non-overlapping sequence detector, however, prevents the
end bit of one sequence from becoming the initial bit of the following sequence.

3 Task No.1 (Implementation of 101011):

3.1 Implementation using Mealy State Machine
3.2 State Diagram (Mealy 101011)
3.3 Mealy Verilog Code (101011)

Test Bench
3.4 Mealy Results (101011)

3.4.1 Console View:

3.4.2 Simulation Waveform (Mealy 101011):

Figure 1: Three output goes high since the sequence is detected two times

Figure 2: Zoomed version of detected sequence as output goes high

 3.5 Discussion and Conclusion:

It is evident that the sequence detection is proceeding properly as when the specified pattern
appears in the input sequence, the output changes to 1. The graphs show that there is no
output delay and that the waveform is identical to Moore's in Figure 2. However, since the
outputs and the new state are assigned together within the same procedural block in this
instance, there should be no delay, therefore this is accurate.

4 Implementation Using Moore State machine

4.1 State Diagram (Moore 101011)
4.2 Moore Verilog Code (101011)

Test Bench
4.3 Moore Results

4.3.1 Console View

4.3.2 Simulation Waveform (Moore 101011):

Figure 3: As it can be seen in the figure the three sequences are detected correctly

Figure 4: Zoomed version

4.3.3 Discussion and Conclusion:

It is clear that the sequence detection process is working well as when the specified
pattern appears in the input sequence, the output changes to 1. The graphs, however,
show that in this instance the delay that should have appeared in the output moving to
state 1 is there. The output is defined in the code to be 1 when state (s6) has emerged,
however according to the Mealay design, the output should change to 1 at the first clock
edge, as seen by the output and the console view.

5 Task No.2 (Implementation of three 1’s):

5.1 Implementation Using Moore State machine

5.1.1 State Diagram (Moore)

5.2 Moore Verilog Code

Test Bench
5.3 Moore Results

5.3.1 Console View

5.3.2 Simulation Waveform (Moore 111):

Figure 5: As it can be seen in the figure the two sequences are detected correctly (3 1’s)

Figure 6: Zoomed version

5.3.3 Discussion and Conclusion:
The correctness of the sequence detection has been observed as when the specified
pattern appears in the input sequence, the output changes to 1. As the graphs
demonstrate. Due to Moore's Law, the output is declared in the code to be 1 when state
(s_3) has emerged, even though it should have done so at the following clock edge.
The console display provides further confirmation that the procedure is correct. The logic
for the code was designed using the same state diagram. Note that the total number of
states is 4, this will be reduced in case of Mealy design in the following section.

6 Implementation Using Mealy State machine

6.1.1 State Diagram (Mealy)
6.2 Mealy Verilog Code

Test Bench
 6.3 Moore Results

6.3.1 Console View

6.3.2 Simulation Waveform

Figure 7: Mealy output for detection of consecutive three one’s

\

Figure 8: Zoomed Version

6.4 Discussion and Conclusion

Moore's architecture likewise functions logically, but with delays, while Mealy's approach
operates flawlessly with appropriate outputs and no delays.
In the case of Mealy, the design was more difficult in Q1, but in Q2 I found the design for
Mealy to be simpler than the design for Moore. This was most likely due to the multi-trigger
state design, for which the fewer outputs significantly reduced the number of fallbacks and
the amount of inter-state relations thinking.
In summary, it was a terrific learning exercise that helped us understand both the
fundamental and more complex ideas behind state machine coding in Verilog.

7 References:
 [1]
“ModelSim ® Tutorial.” [Online]. Available: https://www.microsemi.com/document-
portal/doc_view/131618-modelsim-tutorial.

 [1]
“ISE In-Depth Tutorial,” 2011. [Online]. Available:
https://www.xilinx.com/htmldocs/xilinx13_3/ise_tutorial_ug695.pdf

 [1]
“ISE 10.1 Quick Start Tutorial.” Accessed: Apr. 20, 2022. [Online]. Available:
https://www.eng.auburn.edu/~strouce/class/elec4200/qst.pdf\